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How Do You Route Your Highly Constrained PCBs? (Part 1 of 2)
How routing is performed to meet the design intent of designers and engineers seems to be a topic of constant debate. Is manual routing better than automatic routing? Is designer-guided,...
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What's Good About Allegro PCB Enhanced Object Filtering? See for yourself in...
The 16.6 Allegro PCB Editor release provides enhanced Object Filtering to control object display in the Constraint Manager (CM) Worksheet. This feature enables you to select and filter out objects that...
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Create Optimum Pin Assignments for FPGAs on PCBs - Part 2 of 2
In part 1 of this blog, I discussed a scenario that PCB designers working with FPGA-based boards are often faced with: getting pin assignments from FPGA and/or schematic engineers that can create...
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What's Good About Allegro PCB Editor Shape Contraction and Expansion? Check...
The 16.6 Allegro PCB Editor includes new enhancements to effectively manage shape operations.Read on for more details …Shape Expansion/ContractionThe ability to contract or expand an existing shape(s)...
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What's Good About FSP’s Allegro PCB Editor Board Import? 16.6 Has It!
The Allegro FPGA System Planner (FSP) has the ability in the 16.6 release to import Allegro PCB Editor .brd file contents. Read on for all the great details …To import an Allegro design, you must first...
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What's Good About ADW’s Pull-Down Lists? 16.6 Has a Few New Enhancements!
The 16.6 Allegro Design Workbench (ADW) release now provides the ability to customize the pull-down list values for part property editing. Some classification properties require “freeform” values...
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Customer Support Recommended - Dimensioning in Allegro PCB Editor
Allegro PCB Editor offers drafting and dimensioning features that support electronic design automation (EDA) industry standards that enable you to specify the dimensions of every feature on a board...
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What's Good About Capture’s Update Cache? 16.6 Has a Few Enhancements!
The 16.6 OrCad Capture release now allows you to replace multiple cache parts in one operation. In addition, all options of Replace Cache now work on Update Cache.Read on for more details…In earlier...
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What's Good About AMS Simulator IBIS Model Capability? It’s in the 16.6 Release!
The 16.6 AMS Simulator now provides IBIS model simulation capability:SPICE circuit generation for all IBIS versionsSupport for V-T curvesAnalog simulation of XNets (use Advanced Analysis tools for...
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Why Does Signal Integrity Analysis Need to be Power Aware?
Ever since the I/O Buffer Information Specification (IBIS) committee broke away from the "signal only" mentality and approved the new standard for including power information within the IBIS spec,...
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What's Good About Allegro PCB Editor Embedded Net Name Display? Check Out 16.6!
A new graphical display option in the 16.6 Allegro PCB Editor embeds net names within the cline path, pins, shapes, and flow lines. Useful in just about any PCB application, the display of net names...
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What's Good About Allegro PCB Editor ECSets and Ref Des Values? 16.6 Has a...
Beginning with the 16.6 Allegro PCB Editor, the environment variable UPDATE_ECSET_REFDES is now the default behavior. Read on for more details …Most Electrical Constraint Sets (ECSets) will map based...
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What's Good About DEHDL’s Variant Editor? 16.6 Has Several New Enhancements!
The recent 16.6 QISR-2 for Allegro Design Entry HDL has new capabilities for the Variant Editor.Read on for more details…Dynamic Viewing of Variants in the Schematic EditorA new toolbar and menus have...
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What's Good About FPGA System Planner and Netgroups? 16.6 Has It!
Beginning with the 16.6 SPB release, FPGA System Planner (FSP) can create net groups automatically whenever an interface is instantiated or a protocol is created. These switches control the...
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Signal Integrity Analysis of Serial Data Channels—A Complete Solution Using...
Back in the day, when challenged to transfer data faster, we increased the width of the interface from 8 bits to 16 or from 16 to 32 and so on. The wider the bus got, the more challenging timing...
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Optimize Your PCB Decoupling Capacitors and Remain a Person of Integrity
How much integrity is too much? If your PCB designs apply one or more decoupling capacitors (decaps) per power pin, then you may have too much integrity - power integrity, that is. Your designs are...
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What's Good About AMS Multi-Core Engine Support? It’s in the 16.6 Release!
The 16.6 AMS Simulator (PSpice) release now includes support for multi-core capabilities. There are several runtime options available to enhance the performance of simulation runs.Read on for more...
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What's Good About Capture’s NetGroup Update? 16.6 Has a Few New Enhancements!
The 16.6 release of OrCAD Capture provides a few enhancements in the area of NetGroups.NetGroup membership is visible in the schematic and the schematic printout: You can assign NetGroups through the...
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Customer Support Recommended - Implementing Jumpers in Allegro PCB Editor
Over the time, jumpers have found their importance in multiple applications. The following blog is aimed to provide more insight on their usage and implementation using Cadence Allegro PCB Editor.What...
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What's Good About Allegro PCB Editor New Ratsnest Display Option? Check Out...
The 16.6 Allegro PCB Editor release has a ratsnest display option that is designed to reduce the density of rat display in the workspace. Rats seen as pass-through, ones not terminating to a pin in...
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