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What's Good About Allegro PCB Editor CM Analysis Control? 16.6 Has a Few New...
Beginning with the 16.6 version of Allegro PCB Editor, you can now toggle the Analysis flag directly from the Constraint Manager (CM) column header without using the “Analysis Modes” dialog. Read on...
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What's Good About Allegro/OrCAD/Sigrity Quarterly Incremental Releases...
You’ve no doubt seen announcements (either via customer emails, on the Cadence website, on the Cadence Customer Support portal, etc.) about Quarterly Incremental Releases (QiRs). QiRs have been made...
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Multi-Fabric Planning for Efficient PCB Design
Recently, an article was published in Printed Circuit Design and Fab by Cadence product manager Kevin Rinebold talking about Multi-Fabric Planning for Efficient PCB Design(see page 22 of printed...
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What's Good About DEHDL’s Cross Referencing of Hierarchical Nets? 16.6 has...
The 16.6 Design Entry HDL (DEHDL) Cross Referencer has some new enhancements to report on hierarchical nets.Read on for more details …Just a quick post this week to share with you a couple new...
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What's Good About ADW’s Board File Management? 16.6 Has a Few New Enhancements!
There are two new use models for PCB designers using Allegro Design Workbench (ADW) in 16.6. In 16.5, only a single PCB designer could work on the physical view of the design at one time.Now, the 16.6...
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What's Good About DEHDL “How To” Videos? The Secret's in the 16.6 Release!
While there are several videos available for Allegro Design Entry HDL (DEHDL) in Cadence Online Support as well as in the product installation documentation folder ($CDSROOT/doc), there are times when...
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What's Good About Capture’s Auto Part Reference? 16.6 has a Few New...
The 16.6 release of OrCAD Capture has a couple new productivity enhancements centered around how reference designators are assigned to components in the schematic.Read on for more details …Design Level...
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What's Good About Allegro AMS Simulator PSpice Model Encryption? It’s in the...
With the 16.6 Allegro AMS Simulator (PSpice) release, you now have a new AES 256-bit encryption algorithm. This makes the encryption utility of PSpice and the Model Editor both faster and more robust....
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What's Good About Allegro PCB Editor Show Measure for Dual Units? 16.6 Has It!
The Allegro PCB Editor 16.6 ‘Show Measure’ command now displays results in database and alternate units. Alternate unit display requires the enablement of the user preference variable...
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What's Good About Allegro PCB Editor Offset Routing? 16.6 Has a Few New...
The Add Connect with Offset command in Allegro PCB Editor 16.6 is designed to primarily address the requirement to route with non-standard angles to help minimize impedance discontinuities while...
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What's Good About Allegro PCB Editor IPC 2581 Data Transfer Standard? 16.6...
The 16.6 Allegro PCB Editor now has IPC 2581 data transfer capabilities. Thanks to Ed Hickey – the Allegro Sr. Product Engineering Manager - for preparing this information below.Read on for more...
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What's Good About Allegro PCB Editor Design Partitioning? 16.6 Has Several...
The 16.6 release of Allegro PCB Editor has several new enhancements for team design work (design partitioning) that help reduce the number of .DPF (design partition file) import/export iterations the...
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What's Good About Allegro PCB Editor Dual-Side Contact Components? It’s in...
The use of dual-sided contact components when placed on internal layers of the PCB allows connections to be made from either side of the device. One of the benefits of using this emerging technology is...
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What's Good About Allegro PCB Editor Multiple Constraint Region Assignments?...
Just a short post today.In the 16.6 Allegro PCB Editor release, multiple region shapes can now be assigned to a single region constraint object. Using the General Edit Application mode, pre-select...
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What's Good About Allegro DEHDL Net Renaming? The Secret's in the 16.6 Release!
Just a brief post this week to mention a new capability for Allegro Design Entry HDL (DEHDL) that was made available in the 16.6-QIR4 release.You can now employ net renaming without loss of data:All...
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DDR4 Power-Aware Signal Integrity Adopting Serial Link Simulation Techniques
The signal integrity (SI) prophets had predicted this time would come, and it turns out they were right. The techniques that SI engineers have been using for the past decade to analyze multi-gigabit...
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What's Good About Allegro Design Workbench Team Collaboration? Find Out in...
The Allegro Design Workbench Team Design Option (TDO) offers two (2) specific integrator roles for team design and collaboration:Logical design integrator Responsible for front-end designPhysical...
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Create Ideal Solder Mask Openings Around Bond Fingers with Cadence 16.6 IC...
Normal 0 false false false EN-US X-NONE X-NONEExposing metal through solder mask openings is as necessary as it can be frustrating. For regular arrays and grids of pins of a flip chip, embedding the...
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Customer Support Recommended – Using Test {oints in Allegro Design Entry CIS...
A test point is a location within an electronic circuit that is used to either monitor the state of the circuitry or to inject test signals. Test points have two primary uses:During manufacturing they...
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What's Good About Capture’s Design Rule Checks? 16.6 Has Several New...
The Allegro Design Entry CIS (OrCAD Capture) 16.6 release provides extensions to the Design Rule Checks (DRC) system. The Custom DRC provides the ability to extend the Capture DRC system to...
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