Back in the day, when challenged to transfer data faster, we increased the width of the interface from 8 bits to 16 or from 16 to 32 and so on. The wider the bus got, the more challenging timing became. We added strobes for interface lanes to better manage timing, but faster and wider buses added more complexity. Somewhere around 64 bits and 500 MHz (remember PCI-X 533?), we recognized that the trend could not continue.
Today, with the exception of memory interfaces, multi-gigabit data transfers are accomplished through serial interfaces. Transceivers now include complex adaptive equalization that can only be described through software algorithms. To enable simulation, the industry extended the IBIS modeling specification standard to include an algorithmic modeling interface (AMI).
Cadence's Allegro Sigrity Serial Link Analysis is a full-featured serial analysis solution that includes model extraction, topology generation, and system signal-integrity analysis that supports IBIS-AMI. The die-to-die topology is modeled in SystemSI. An impulse response of the channel is convolved with a large bitstream using high-capacity channel simulation, and then the channel analysis results can be compared to industry-standard compliance tests, such as PCI Express (PCIe) 3.0.
Grab a cup of coffee and watch the demonstration of our complete solution that addresses serial link analysis. These simulation results can be compared to PCIe 3.0 requirements using our compliance kit that ships withAllegro Sigrity Serial Link Analysis.
While many signal-integrity engineers focus on final system verification, you can see from the demonstration the advantages of using the serial link analysis technology early in the design cycle. While most would say that an 8.0Gbps channel such as PCIe 3.0 should be implemented in a flip-chip package, this demonstration shows the flip-chip versus wirebond quality differences. Given the results, an enterprising signal integrity team may want to continue tweaking the channel and transceiver in hope that they can implement PCIe 3.0 in a lower cost package and increase profits for their company.
Tell us about your experiences using SystemSI and Cadence Sigrity modeling and extraction technology!
Team Allegro