Ever since the I/O Buffer Information Specification (IBIS) committee broke away from the "signal only" mentality and approved the new standard for including power information within the IBIS spec, there has been a lot of buzz in the industry about performing power-aware signal integrity analysis. Effectively this would mean combining both signal and power integrity analysis into one.
But why does it matter? Users that simulate with ideal power and ground probably think they have been getting along okay. And then there are those that are willing to brave into the world of transistor-level models and hand-generated SPICE netlists that have been able to perform a certain level of signal integrity analysis that includes non-ideal power and ground effects.
But what some say has been missing is a system simulation environment that connects interconnect models together across the various fabrics, such as fast and accurate power-aware IBIS models that connect to the non-ideal power and ground planes. And the system simulation cannot stop with just power-aware I/O models. The interconnect models must include signal, power, and ground, as well as the coupling between. Every fabric between the driver and the receiver (chip, package, and PCB) requires power-aware extraction and the hooks to connect to the neighboring fabrics.
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Fortunately, such an environment exists today with Allegro Sigrity SI when utilizing the Power-Aware SI Option. Users of this technology can create power-aware IBIS models, extract PCB interconnect models with coupled signal, power, and ground, and connect these models together to chip, package, and connector models. Once extracted and connected, system-level (I/O buffer to I/O buffer) simulation is available that includes all the required effects. This simulation demonstrates performance during conditions where simultaneously switching signals cause power and ground planes to fluctuate from their ideal voltages.
So, to answer the original question as to why "power-aware" is important... Ideal power provides a false sense of security. You may build a product with meta-stable timing and end up spending hours in the lab trying to debug the problem. A little power-aware signal integrity analysis could have identified the problem before the design was built and led you to a solution without all the hours in the lab and the cost and time it takes to re-spin a design.
For a comprehensive demonstration of how simultaneously switching signals on a DDR interface can be accurately "power-aware" analyzed, please watch the 12-minute movie below.
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Let us know your experiences using power-aware models versus ideal power models when using signal integrity tools.
TeamAllegro
Image may be NSFW.Clik here to view.
Image may be NSFW.Clik here to view.
