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BoardSurfers - Guest Roll: Anatomy of a Good Testcase

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BoardSurfers: Cadence Allegro BlogRik Lee, the author of today's post, is a PCB Designer with more than 35 years experience in the PCB industry, 25+ of those with the Cadence® Allegro® tools. Currently working with the Samtec, he has previously worked for both Cadence and EMA, focusing on back-end PCB layout tool support. 

You come across an issue when using the tools, but you don’t understand why. Being able to troubleshoot an issue, and if needed provide a reproducible testcase to a peer or a Cadence AE, is the first step to resolving the issue.

If you have tried using Tools – Database check and that does not resolve the issue you will need to dig a bit deeper. When debugging the issue make sure it is reproducible. Also, are you on the latest release of the software? You can review the Readme_CCR.txt file to see if a similarly named issue has been resolved. This file can be found on the downloads.cadence.com site for the release that you are using.

Assessing whether this happens in all databases is one of the first steps to take. If needed, there are example databases which you can use for debugging or demonstrating an idea in the \share\pcb\examples\board_design directory of the install hierarchy.

If you can start the tools and see that the issue reproduces, you are well on your way to resolving the issue or helping a peer \ Cadence help you. You can note the steps taken to get to the issue or, even better, record a script that can be used to reproduce the issue. Open the drawing and select File – Script. Add a name for the script and then click Record.

Repeat the steps that show the issue and then stop the script by either clicking Stop in the Scripting dialog or enter stop at the command line. If you would like, you can add prompts to the drawing to describe what you are seeing. By typing at the layout editor command line, for example:

    confirm "Note how the clines spread too far."

Will produce this in the application:

When using this in a script, you will need to edit the script in a text editor to remove the fillin yes statement that follows your confirm statement or the layout editor will close the dialog.

When creating a testcase, leave only the layers that are affected enabled for display and zoom into the area of interest. While you may be intimately familiar with the issue and area of the design, a person that is seeing this for the first time would not be.

If the problem is a crash issue, you can use the journal file allegro.jrl and convert the journal into a script that can be used on the database. To best use this functionality, you should set the environment variable journal_nobuffer which is found in the file_management/journals category of User Preferences Editor before recording the script. Setting this variable changes the output of allegro.jrl to unbuffered. The advantage of unbuffered output is that sometimes with program crashes more lines are written to the journal file. I’d suggest only using this variable when you know you want to use allegro.jrl as a script, as it will slow the tool down.

To convert an allegro.jrl file into a script you can click Generate from the scripting dialog and browse to the allegro.jrl file or, you can open a command window in the directory that the journal file is stored and enter:

    j2script allegro.jrl textcase.scr

You may need to open the script file and remove the last few lines so the layout editor does not exit when replaying the script. Once you have a script that reproduces the problem, the next step would be to verify whether it’s a core tool issue or perhaps something in your environment that is the root cause. There are several methods you can use to perform this step which involves starting the tools without your environment variables.

One method is to rename your pcbenv directory. You can determine where your pcbenv directory is by opening a Windows file manager/Explorer window and at the top in the address line type:

    %home%

This will navigate to your HOME directory. Rename pcbenv to old_pcbenv. Restart the tools and none of your environment settings are used. Once you have finished with the debugging of the issue, you will need to delete the newly created pcbenv and rename old_pcbenv back to pcbenv to restore your environment.

The second method would be to open a command window where the drawing is located and type:

    allegro -safe

This will start the layout editor without any of your environment settings as if it’s was a fresh installation with no need to rename directories.

You then check to see if the issue will reproduce. If it does, you can be confident that others will be able to see the issue and provide a resolution or pass the issue onto Cadence engineering so that they can look into the issue.

What should be included when asking others to review a testcase?

The files below are needed when you are trying to show someone a problem you're having:

  1. The Allegro database, zoomed into the area of interest, with only those layers needed to see the issue enabled in the color dialog. If you are concerned with IP, use File – Export – Strip design… (strip_design command) to rename and/or delete items in the database.
  2. The allegro.jrl file.
  3. The variables for both the operating system (OS) and the layout editor:
    • To retrieve the OS variables, open a command window and type set >OS_env.txt. this will produce an OS_env.txt file.
    • To retrieve the layout editor variables, use the tool and select Tools – Utilities – Env variables. Save the results to a file named allegro_set.txt.
  4. Any files that are needed to support the layout editor tools. For example:
    • Artwork: photoplot.log, art_param.txt, and art_aper.txt (if applicable).
    • Import issue: any netlist files, DXF along with the conversion files, IDX, or IDF files.
  5. Any screenshots you would like to add. As they say, a picture is worth a thousand words. These can be added to a Word document that describes the issue if you need to provide text for context, or just included as the image files with reasonable names to tell what they show.

Making sure that the person you send the data to can see what you’re seeing gets you an answer much quicker, so taking the few minutes up front can save you hours of back-and-forth time later on when that person needs to come back to you with questions about how to reproduce your problem.

Rik Lee


BoardSurfers: Avoid Iterations with Your Manufacturing Partner – Detect and Address DFM Issues in the Design Phase using DesignTrue DFM

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 Some things are rare, good or bad, but they do happen from time to time. And, some happen so regularly, we often take them for granted if good or learn to live with them if bad. But should we? For example, you send out your design for fabrication and the CAM (Computer Aided Manufacturing) engineer runs a high-end Design for Manufacturability (DFM) analysis software. The CAM engineer sees DFM issues (almost always!). Now, there are three scenarios: the CAM engineer updates the design and informs you; the CAM engineer updates the design but forgets to inform you; or the worst case, the CAM engineer does not update the design at all thinking the issue was minor.

In the scenario that the CAM engineer informs you, you go ahead and make changes to your design and you are good, though it involves inconvenient rework. But in the scenario that the CAM engineer does not inform you, you are not good; the designs do not match, and your design has issues that you will never know. The scenario where the CAM engineer forgets to update the design needs no discussion, I suppose the loss of time and money is obvious enough.

In any case, you are either inundated with manufacturing issues in the middle of another project or your design is riddled with manufacturing issues and you are not aware; annular ring issues, copper spacing issues, differential pairs that neck down and shouldn’t, void around the via - the traces run right the edge of the cutout, plane issues - vias half in half out, and back drilling issues – spacing checks of drill hole to metal (annular ring metal remaining), to name just a few.

So, the easiest and the most obvious thing to do is to run DFM analysis and correct any issues before sending the boards off to the fabricators. Well, you like this solution and create an internal sign-off group to address any manufacturing issues (the conventional design for fabrication flow). But, are you then not spending time reworking the design late anyway? And add to that the fact that the designer is not running DFM but correcting identified problems? So, it seems this flow, which we shall call the Conventional Design for Fabrication Flow, is not the most ideal solution.

That’s why it is a good idea to perform DFM analysis early in the cycle and by the designer. It was a difficult proposition earlier, an easier said than done thing. But no more. The DesignTrue DFM feature of Allegro® PCB Editor has made it available in an easy to use format.

DesignTrue DFM Design Fabrication Flow

In PCB Editor, manufacturability checks are available from the software itself - you don’t need a separate software and wait till the end to identify and correct issues. The sign-off phase still exists using tools such as Allegro®/OrCAD® Manufacturing Option, but with DesignTrue DFM, the iterations and the time required to produce fabrication data decreases multiple times. DesignTrue DFM identifies issues that might come up when boards are being manufactured, that is when boards are being fabricated and assembled. So, you have two main types of analyses, Design for Fabrication (DFF) and Design for Assembly (DFA). We will talk about them in details in our upcoming blogs.

DATA Pulse: In Search of the Perfect Environment—Configuring Allegro EDM

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  Ah, the office temperature – that eternal debate. As in many offices, ours has some people who feel that they're in the Sahara Desert, others who bundle up like they're in Antarctica, a few who just don't care about the temperature, and some who can't quite figure out if they're ever comfortable, like Goldilocks. There is however no 'perfect' temperature. So many variables impact the physical environment of the office – one's activity level, humidity, the outside temperature.

It's the same with Allegro EDM, a client-server suite of applications. There is no 'perfect' environment that suits everyone. Its configuration depends on several factors – Does your company have multiple sites? Do they span geographic regions? How many users do you have per site? Do you intend to work across releases? For example, your X server is in 16.6 and your Y server is in 17.2. What is the average Designer Server’s load at a site? Do you want redundant Designer Servers? What's the network performance in each site? What kind and data size do you manage? Do you plan to scale up your setup? What is your budget? What is your existing library and design data management setup? What sort of hardware do you already have?

Using Allegro EDM's Configuration Manager, a wizard for ECAD administrators, configure the EDM server, clients, and sites and move to the latest hotfix versions. Also customize workspaces, manage utility and library distribution configurations, and compare two sites and merge differences if needed. 

After you configure your EDM servers and clients, view the Configuration Manager map for the locations of various servers around the world and their status.

Particularly helpful for troubleshooting, to reduce an ECAD administrator's response time, and to improve server uptime, you can check on the health of the EDM server from the Configuration Manager: which version of EDM is installed, whether the server is up and running, which software components are installed, and hardware statistics. 

When configuring EDM, you can also decide whether to have the EDM server log various kinds of messages—errors, warnings, and information messages—and whether you want to be notified of these through e-mails. As an ECAD administrator, this can help you more easily monitor the health of the server. Messages are logged in the \<pcbdw_lib>\server\log\adwserver.out file.

Once you configure Allegro EDM, use <startworkbench>.bat to open Allegro EDM Flow Manager. Among other things, Flow Manager is a cockpit through which you can launch all EDM applications. 

Want to know more? Configure Allegro EDM 17.2 using a sample database available with the following Cadence Rapid Adoption Kit (RAK): Configuring Allegro Engineering Design Management (EDM) with a Default Database. Cadence RAKs are easily available by going to support.cadence.com and selecting Resources — Rapid Adoption Kits. So, get yourself a cup of coffee, gaze out at the view from your window, then hit the books!

Related Resources

BoardSurfers: Designing a Rigid-flex Board using PCB Editor

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BoardSurfers: Cadence Allegro BlogWhether you are designing the latest pace-maker or a LED strip, you have definitely pondered awhile about rigid PCBs and flex PCBs. You might have gone through a pile of literature, called up friends who have already done it (after all flex PCBs have been around for more than half a century now), and deliberated with your team to finally settle on a rigid-flex PCB. Well, what had started as a cutting-edge requirement to enable humanity's space dreams is today almost ubiquitous - think smart, wearable devices. There are many reasons why rigid-flex has become common, and the reasons are based on practical requirements of the time: dense designs, ever-decreasing size of devices, signal integrity requirements, and so on. But all these (size, density, etc) require a flex design, which increases the cost; and you want a balance -  you go for rigid-flex.  In the shortest possible way, quoting an earlier blog (not reinventing the wheel), here is the 'why' of choosing rigid-flex: "For nearly all applications, customers continue to demand smaller, lighter, and more cost-effective products. Competitive pressures also force designers to bring these new products to market at an ever-increasing rate. Designers can deploy flexible PCB materials (flex/rigid-flex) to meet challenging form-factor requirements, eliminate connectors, and improve performance. "

But as soon as a solution becomes popular, we start looking at enhancements to make it even better and optimize it further. Even in the rigid-flex PCB world, we have come a long way. To again quote from an earlier blog, Making Rigid-Flex PCB Design a Little Easier,  "Designers once integrated the flexible portion of their circuitry as a connector from one rigid board to another. But now that there are even more stringent area demands, designers are now placing components on the flexible circuit area."  Along with the new possibilities, applications, and requirements comes the part where we at Cadence can contribute - enabling you as designers in the most cost-effective and productive way possible.  

Rigid-Flex PCB

So how does PCB Editor enable you to design a rigid-flex PCB? Well, in many ways! But I am listing a few of the more important ones here.

Rigid-Flex Transformation (Bending)

Not only do you have the bend area capability on the 2D workspace, but you can also transform your rigid-flex designs from a flat 2D state into a transformed 3D state. You can visualize how your designs will look like when they are in their intended state. Oh, and the centering feature of 3D Canvas automatically recenters rigid-flex designs on the canvas after a bend operation.

Multiple flex laminates supporting flex circuit coverlays

The soldermask layer in rigid PCBs is no good for flex PCBs. You now need a flex circuit coverlay.   So, Cross Section Editor supports the entry of non-conductor layers -  mask and coating layers used in rigid, flex or rigid-flex applications. You will usually add these layers above the Top or below the Bottom surfaces but can also add them within the core stackup to accommodate multiple independent flex laminates. The Cross Section Editor provides total thicknesses for each stackup in terms of accumulated conductor layers as well as an option with mask layer thicknesses included. 

The multi-cross section support is complemented by an option to output a multi stackup table. The table supports entries for all conductor and non-conductor layers, material, and thicknesses.

 And, yes, the surface finish options have been enhanced too. So you can choose the right finish from the options available. 

Zone management for rigid and flex

Now that you have a design that is a mix of rigid and flexible parts, you need a capability to manage the physical areas pertaining to these.

A physical zone is used to map an area of the design to one of the stackups created in the Cross Section Editor. Zones can be rigid or flex areas consisting of varying layers. Rigid zones, for example, might be comprised of 10 conductor layers and soldermask whereas a flex zone may contain 2 conductor layers plus several mask layers such as coverlay, adhesive, or stiffeners.

Zones automatically include associated keepouts and optional constraint regions and rooms. Any part of the board that is outside of any zone will use the Primary Stack-up for its layer cross-section. 

Checking Coverage and Clearances - Interlayer Checks

When you are designing a rigid PCB, you verify the proper clearance and coverage for masks and surfaces. Rigid-flex designs not only have the same mask and surface finish requirements but the addition of bend areas, stiffeners, and so on, that require special clearances or overlaps of materials, spacing, and design features. So you need (and get) the interlayer checks capabilities. What's more, you get the power of in-design checks, as mentioned by Ed Hickey in the white paper Automating Inter-Layer In-Design Checks in Rigid-Flex PCBs: "By allowing you to perform DRCs for various non-electrical flex layers, the tool (PCB Editor) helps to save time and avoid respins. The tool also supports real-time concurrent team design, so multiple PCB designers can work on the same PCB design database. "

Conclusion

So far so good but words are only words, why not try it out? Walk the walk? Click here for a Rapid Adoption Kit with detailed step-by-step procedures on the Rigid-Flex functionality, including various important aspects not discussed in this blog, such as IPC-2581 Layer Function support, multi stack up grid, and manufacturing preparation support. The Rapid Action Kit is accompanied by a database that you can use to perform the exercises in the document. 

Note: The above link can only be accessed by Cadence customers who have a valid login ID for https://support.cadence.com

BoardSurfers: Capturing Design Intent for Automatic Routing in PCB Editor

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BoardSurfers: Cadence Allegro BlogImagine you are designing a complex board with thousands of interconnects and all the usual complexities inherent in a dense design that is also highly constrained. Well, it's easy, the 'imagine' part; and you don't even have to try like John Lennon had crooned in his Imagine song, because most probably you are actually designing one right now that is dominated by bussed interconnect. And most probably your mind is stretched to its limit keeping track of the thousands of connections across several layers and a variety of constraints. 

PCB design dominated by bussed interconnect

What if I now tell you that you can use PCB Editor to do the following:

  • Intelligently plan and autoroute interconnect
  • Capture all electrical constraints and designer intent
  • Route your design using flow planning to enable a “correct the first time” execution
  • Boost performance and productivity significantly
  • Reduce cycle time reductions during placement and routing
  • Shorten overall design process in contrast to today’s manual planning and routing methods

In one of our earlier blogs discussing rigid-flex PCBs, we had mentioned how flexible PCBs were around for more than half a century but was difficult to implement because tools till now were not supporting an easy implementation. Same is the case with complex interfaces; we were living on with the limitations, struggling and reworking to make do with what we had. No more! You can now use PCB Editor to capture all electrical design intent and designer preference before starting with detailed routing. You can also rest assured that routing will implement the interconnect flow exactly. Of course, you will significantly reduce cycle time during placement and routing because of the automated process. 

PCB Editor lets you handle the interconnects graphically by abstracting the interconnect data, making it easier to define and capture your routing intent. And, yes, you don't need to overload your short-term working memory while routing, because the advanced autorouter keeps track of the hierarchies and routing spaces. The autorouter will validate design intent, as you are working, to enable you to make the right decisions. Also, by identifying interconnect issues early in the design, the autorouter makes you aware of issues that might have lingered on forcing you to rework. And the best part? You don't have to go back to the beginning if you recognize an issue, rather you can back up to any of a previous planning stage.

If you are already excited and want to know more about interconnect flow planning and other PCB Editor features that help you increase productivity, click here for a Rapid Adoption Kit with detailed step-by-step procedures on design planning of high-speed designs.

Note: The above link can only be accessed by Cadence customers who have a valid login ID for https://support.cadence.com

BoardSurfers - Aerials and Bails: How to Rename Reference Designators Using Batch Command

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Components on a board are often placed per their functional group and hence their reference designators are all jumbled up. It is a common practice to rename reference designators before sending out the design data to manufacturers. Reference designator...(read more)

BoardSurfers: Five Ways to View Your Design in 3D Canvas

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Five simple yet effective ways to increase efficiency by selecting the right objects you want to model, say, all the pins or a subset of the pins in a design.(read more)

DATA Pulse: Playing Favorites with Parts—Influencing Design Part Selection with a Preferred Parts List

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  Life is full of decisions - what college major to opt for, which career path to follow, whether to move cities for a job or stay put, whether to switch career paths midstream for a more fulfilling life. You know what I mean.

As a librarian, your professional life is as full of choices and decisions to be made. OK, so maybe they're not as life changing as the ones I've just listed, but they're important. However, it's a challenge. You have hundreds of parts to choose from and some are duplicated. You're struggling with legacy systems, missing, inaccurate, or inconsistent data, poor part data quality. You've gulped down more cups of coffee than you'd care to count, and you finally clutch your head and make less than optimum part selections.

Now imagine that you could reduce parts-related costs, eliminate part duplication, designate and limit parts used for new designs, select optimum parts for functional applications, and minimize the number of managed parts – all while maintaining flexibility to effectively use new technology. Sounds like a tall order, doesn't it? But it can be done.

You can significantly improve parts management, lower costs, and streamline part selection by using Preferred Parts Lists (PPLs). While procurement, components engineering, and manufacturing teams define preferred parts, as the librarian, you can assign PPLs in EDM.

With the use of PPLs, your enterprise improves the quality and performance of new designs by selecting and using the best available parts of proven reliability and performance that adhere to required regulations. You avoid incompatibility (manufacturing, environment), and minimize sole-source risks and cost variability.

You also minimize costs and avoid duplication by using fewer parts because of smaller inventories, which maximizes your purchasing power and results in fewer purchase orders. Furthermore, the use of PPLs minimizes lead times by strengthening the supply chain and reducing engineering and procurement cycle time.

Even better, standardization simplifies the mundane but necessary tasks of:

  • Selecting and reviewing new parts and suppliers
  • Certifying and tracking new parts and suppliers
  • Creating and maintaining design libraries
  • Procuring, storing, and managing parts
  • Resolving part supplier issues

You and your designers can easily choose parts based on parameters such as preferred suppliers, industry standards, proven performance, reliability, durability, quality, assured availability, continuity of supply, lead time, capacity, best value to enterprise, and so on.

But how do you manage preferred parts? You could develop a strategy by way of:

  • Mandated use of preferred parts
  • Continuous process improvement
  • An option to remove non-preferred parts from the preferred parts list

In Allegro EDM, a librarian can create multiple PPLs and have hierarchical PPLs (parent-child relationship). For example, you can have a parent PPL for RF parts and multiple child PPLs for 1GHz, 2GHz, 3GHz RF parts.


To make it easier for designers to quickly distinguish between parts, assign attributes to PPLs such as color. For example, use different colors for power PPLs and PPLs for capacitor. In Part Information Manager, part search results display the color of a PPL thus speeding up engineers' part selection process.

You can associate parts with PPLs in any of the following ways:

In Allegro EDM Database Administrator

Through Database Editor

Using Allegro EDM Data Exchange for batch assignment of parts to PPLs. Using Data Exchange, you can also, if needed, import an already existing PPL from a non-Cadence data source.

Designers can associate one or more PPLs to a design using Allegro EDM Project Wizard. PPL assignment can be restricted, that is the PPL Only mode. In this case, only parts in the PPL can be added to the design. Or, you can use the non-restricted mode, that is, PPL Plus, where parts not in the PPL can be added to a design, but with a warning.

Not working with an Allegro EDM project but want to define PPLs? Easy. Use the project_ppl directive in the project CPM file. Furthermore, ECAD administrators can define PPLs for an entire site using the the same directive in the site.cpm file.

Making decisions about parts will always involve juggling priorities, budgets, timelines, and so on, but PPLs can make your life as a librarian easier. It's said that playing favorites is bad, but in this case, go ahead! It's good.


BoardSurfers: PCB Electronics - Six Things to Do Before You Actually Place Components on a PCB

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It's a PCB you are designing. Where do you start? What can you do to make your process more productive and efficient? Are you feeling at lost? Worry not. We will talk about the six things you do before you start placing components on the board, and, of course, if you use PCB Editor, there is the Design Workflow guide to ease the board design process for you.(read more)

BoardSurfers: PCB Design Technique for Designing a Small RF Section in a Digital Board

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Are you designing a 5G or radar application, or for that matter any application, that requires RF components? Are cost, size-reduction, and performance improvement major concerns for you? Most probably they are. Here we talk about an innovative solution for mixed-signal RF designs using Cadence layout editors.(read more)

BoardSurfers - Guest Roll: Anatomy of a Good Testcase

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BoardSurfers: Cadence Allegro BlogRik Lee, the author of today's post, is a PCB Designer with more than 35 years experience in the PCB industry, 25+ of those with the Cadence® Allegro® tools. Currently working with Samtec, he has previously worked for both Cadence and EMA, focusing on back-end PCB layout tool support. 

You come across an issue when using the tools, but you don’t understand why. Being able to troubleshoot an issue, and if needed provide a reproducible testcase to a peer or a Cadence AE, is the first step to resolving the issue.

If you have tried using Tools – Database check and that does not resolve the issue you will need to dig a bit deeper. When debugging the issue make sure it is reproducible. Also, are you on the latest release of the software? You can review the Readme_CCR.txt file to see if a similarly named issue has been resolved. This file can be found on the downloads.cadence.com site for the release that you are using.

Assessing whether this happens in all databases is one of the first steps to take. If needed, there are example databases which you can use for debugging or demonstrating an idea in the \share\pcb\examples\board_design directory of the install hierarchy.

If you can start the tools and see that the issue reproduces, you are well on your way to resolving the issue or helping a peer \ Cadence help you. You can note the steps taken to get to the issue or, even better, record a script that can be used to reproduce the issue. Open the drawing and select File – Script. Add a name for the script and then click Record.

Repeat the steps that show the issue and then stop the script by either clicking Stop in the Scripting dialog or enter stop at the command line. If you would like, you can add prompts to the drawing to describe what you are seeing. By typing at the layout editor command line, for example:

    confirm "Note how the clines spread too far."

Will produce this in the application:

When using this in a script, you will need to edit the script in a text editor to remove the fillin yes statement that follows your confirm statement or the layout editor will close the dialog.

When creating a testcase, leave only the layers that are affected enabled for display and zoom into the area of interest. While you may be intimately familiar with the issue and area of the design, a person that is seeing this for the first time would not be.

If the problem is a crash issue, you can use the journal file allegro.jrl and convert the journal into a script that can be used on the database. To best use this functionality, you should set the environment variable journal_nobuffer which is found in the file_management/journals category of User Preferences Editor before recording the script. Setting this variable changes the output of allegro.jrl to unbuffered. The advantage of unbuffered output is that sometimes with program crashes more lines are written to the journal file. I’d suggest only using this variable when you know you want to use allegro.jrl as a script, as it will slow the tool down.

To convert an allegro.jrl file into a script you can click Generate from the scripting dialog and browse to the allegro.jrl file or, you can open a command window in the directory that the journal file is stored and enter:

    j2script allegro.jrl textcase.scr

You may need to open the script file and remove the last few lines so the layout editor does not exit when replaying the script. Once you have a script that reproduces the problem, the next step would be to verify whether it’s a core tool issue or perhaps something in your environment that is the root cause. There are several methods you can use to perform this step which involves starting the tools without your environment variables.

One method is to rename your pcbenv directory. You can determine where your pcbenv directory is by opening a Windows file manager/Explorer window and at the top in the address line type:

    %home%

This will navigate to your HOME directory. Rename pcbenv to old_pcbenv. Restart the tools and none of your environment settings are used. Once you have finished with the debugging of the issue, you will need to delete the newly created pcbenv and rename old_pcbenv back to pcbenv to restore your environment.

The second method would be to open a command window where the drawing is located and type:

    allegro -safe

This will start the layout editor without any of your environment settings as if it’s was a fresh installation with no need to rename directories.

You then check to see if the issue will reproduce. If it does, you can be confident that others will be able to see the issue and provide a resolution or pass the issue onto Cadence engineering so that they can look into the issue.

What should be included when asking others to review a testcase?

The files below are needed when you are trying to show someone a problem you're having:

  1. The Allegro database, zoomed into the area of interest, with only those layers needed to see the issue enabled in the color dialog. If you are concerned with IP, use File – Export – Strip design… (strip_design command) to rename and/or delete items in the database.
  2. The allegro.jrl file.
  3. The variables for both the operating system (OS) and the layout editor:
    • To retrieve the OS variables, open a command window and type set >OS_env.txt. this will produce an OS_env.txt file.
    • To retrieve the layout editor variables, use the tool and select Tools – Utilities – Env variables. Save the results to a file named allegro_set.txt.
  4. Any files that are needed to support the layout editor tools. For example:
    • Artwork: photoplot.log, art_param.txt, and art_aper.txt (if applicable).
    • Import issue: any netlist files, DXF along with the conversion files, IDX, or IDF files.
  5. Any screenshots you would like to add. As they say, a picture is worth a thousand words. These can be added to a Word document that describes the issue if you need to provide text for context, or just included as the image files with reasonable names to tell what they show.

Making sure that the person you send the data to can see what you’re seeing gets you an answer much quicker, so taking the few minutes up front can save you hours of back-and-forth time later on when that person needs to come back to you with questions about how to reproduce your problem.

Rik Lee

BoardSurfers: PCB Design Technique for Designing a Small RF Section in a Digital Board

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Are you designing a 5G or radar application, or for that matter any application, that requires RF components? Are cost, size-reduction, and performance improvement major concerns for you? Most probably they are. Here we talk about an innovative solution for mixed-signal RF designs using Cadence layout editors.(read more)

BoardSurfers: PCB Electronics - Component Placement - Get Set and Go!

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How do you place components on a PCB design? Manually? Or quickly using automation? Is there a way to rotate or mirror components while placing them? Is there a way to determine the congested areas or the flow within blocks even while placing components? How do you ensure the placed components are aligned? How o you verify all is well with the board? Read on for the answers.(read more)

BoardSurfers: PCB Electronics - Electrical Constraints

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Whether it's NASA's space missions or a school camping trip; building a cutting-edge, reusable rocket system or baking a simple lemon tart - planning is a must to avoid disasters, or at least to get a predictable output. So is the case with PCBs. You want to plan ahead to avoid design mistakes that can cost you money and time. And that's where constraints come handy.(read more)

DATA Pulse: Track Your Components—Efficient Library and Design Data Management

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 Ever noticed how some objects always mysteriously disappear? It's like they have their own legs. Or maybe, secretly, they thirst for adventure and go wandering off. Socks for example. Why does one twin always disappear after a round in the washing machine? After a few months, you just have a sad pile of lonely, orphaned socks in a variety of colors. Pens are equally guilty. They're always disappearing. Pen caps are even worse. Car keys. Passports.

And can there be something worse than not finding something? Yes. Imagine this: you've planned a vacation abroad, booked your plane tickets, and you're ready to go. Then, a week before you leave, you look for your passport. A frantic hunt ensues. Then you find it, but it will expire within six months of your travel date. Arghh.

ECAD engineers are all too familiar with that feeling of fruitless searches. Then they find the component they're looking for but what do you know? It's approaching its end of life. Without the right tools, mismanagement of ECAD data is easy. Imagine a scenario where you released a product but some error forces you to revise your design. Think of all the rework.

Instead, what if you had an efficient library and design data management lifecycle process that could do the following:

  • Ensure a common parts repository, from which parts can be distributed across geographical regions
  • Ensure data consistency
  • Allow the sharing of ECAD libraries across multiple sites
  • Provide dynamic part-related information, such as the following, from PLM systems in your existing setup:
  • Compliance (RoHS, WEEE, ELV)
  • Part datasheets
  • Cost
  • Lifecycle (EOL, approaching EOL)
  • Provide searchable property support with well-classified objects
  • Provide for the definition of Alternate Manufacturer Parts Lists

Allegro EDM's library management solution helps you streamline your ECAD library data management process, thus helping you to complete design projects on time, within budget, and reducing the possibility for errors.
  

So, why wait? Learn how to efficiently manage your ECAD data libraries using the Allegro Library Manager 17.2 Rapid Adoption Kit (RAK). The RAK demonstrates basic operations in the library development flow.

RAKs are easily available by going to support.cadence.com and selecting Resources — Rapid Adoption Kits. So, strap on headphones, tune out all distractions, and get started.


DATA Pulse: In Search of the Perfect Environment—Configuring Allegro EDM

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  Ah, the office temperature – that eternal debate. As in many offices, ours has some people who feel that they're in the Sahara Desert, others who bundle up like they're in Antarctica, a few who just don't care about the temperature, and some who can't quite figure out if they're ever comfortable, like Goldilocks. There is however no 'perfect' temperature. So many variables impact the physical environment of the office – one's activity level, humidity, the outside temperature.

It's the same with Allegro EDM, a client-server suite of applications. There is no 'perfect' environment that suits everyone. Its configuration depends on several factors – Does your company have multiple sites? Do they span geographic regions? How many users do you have per site? Do you intend to work across releases? For example, your X server is in 16.6 and your Y server is in 17.2. What is the average Designer Server’s load at a site? Do you want redundant Designer Servers? What's the network performance in each site? What kind and data size do you manage? Do you plan to scale up your setup? What is your budget? What is your existing library and design data management setup? What sort of hardware do you already have?

Using Allegro EDM's Configuration Manager, a wizard for ECAD administrators, configure the EDM server, clients, and sites and move to the latest hotfix versions. Also customize workspaces, manage utility and library distribution configurations, and compare two sites and merge differences if needed. 

After you configure your EDM servers and clients, view the Configuration Manager map for the locations of various servers around the world and their status.

Particularly helpful for troubleshooting, to reduce an ECAD administrator's response time, and to improve server uptime, you can check on the health of the EDM server from the Configuration Manager: which version of EDM is installed, whether the server is up and running, which software components are installed, and hardware statistics. 

When configuring EDM, you can also decide whether to have the EDM server log various kinds of messages—errors, warnings, and information messages—and whether you want to be notified of these through e-mails. As an ECAD administrator, this can help you more easily monitor the health of the server. Messages are logged in the \<pcbdw_lib>\server\log\adwserver.out file.

Once you configure Allegro EDM, use <startworkbench>.bat to open Allegro EDM Flow Manager. Among other things, Flow Manager is a cockpit through which you can launch all EDM applications. 

Want to know more? Configure Allegro EDM 17.2 using a sample database available with the following Cadence Rapid Adoption Kit (RAK): Configuring Allegro Engineering Design Management (EDM) with a Default Database. Cadence RAKs are easily available by going to support.cadence.com and selecting Resources — Rapid Adoption Kits. So, get yourself a cup of coffee, gaze out at the view from your window, then hit the books!

Related Resources

DATA Pulse: Track Your Components—Efficient Library and Design Data Management

$
0
0

 Ever noticed how some objects always mysteriously disappear? It's like they have their own legs. Or maybe, secretly, they thirst for adventure and go wandering off. Socks for example. Why does one twin always disappear after a round in the washing machine? After a few months, you just have a sad pile of lonely, orphaned socks in a variety of colors. Pens are equally guilty. They're always disappearing. Pen caps are even worse. Car keys. Passports.

And can there be something worse than not finding something? Yes. Imagine this: you've planned a vacation abroad, booked your plane tickets, and you're ready to go. Then, a week before you leave, you look for your passport. A frantic hunt ensues. Then you find it, but it will expire within six months of your travel date. Arghh.

ECAD engineers are all too familiar with that feeling of fruitless searches. Then they find the component they're looking for but what do you know? It's approaching its end of life. Without the right tools, mismanagement of ECAD data is easy. Imagine a scenario where you released a product but some error forces you to revise your design. Think of all the rework.

Instead, what if you had an efficient library and design data management lifecycle process that could do the following:

  • Ensure a common parts repository, from which parts can be distributed across geographical regions
  • Ensure data consistency
  • Allow the sharing of ECAD libraries across multiple sites
  • Provide dynamic part-related information, such as the following, from PLM systems in your existing setup:
    • Compliance (RoHS, WEEE, ELV)
    • Part datasheets
    • Cost
    • Lifecycle (EOL, approaching EOL)
  • Provide searchable property support with well-classified objects
  • Provide for the definition of Alternate Manufacturer Parts Lists

Allegro EDM's library management solution helps you streamline your ECAD library data management process, thus helping you to complete design projects on time, within budget, and reducing the possibility for errors.
  

So, why wait? Learn how to efficiently manage your ECAD data libraries using the Allegro Library Manager 17.2 Rapid Adoption Kit (RAK). The RAK demonstrates basic operations in the library development flow.

RAKs are easily available by going to support.cadence.com and selecting Resources — Rapid Adoption Kits. So, strap on headphones, tune out all distractions, and get started.

BoardSurfers: PCB Electronics - Defining and Applying Physical and Spacing Constraints

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If you get frequent calls from your fab houses or your customers regarding your product, or if your schematic, layout, and packaging engineers spend a lot of time exchanging notes about their requirements not being met, resulting in back and forth of designs, or if you believe, like most of us do, that a product should do what it was designed to do, constraints are your friends. (read more)

BoardSurfers - Guest Roll: Anatomy of a Good Testcase

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BoardSurfers: Cadence Allegro BlogRik Lee, the author of today's post, is a PCB Designer with more than 35 years experience in the PCB industry, 25+ of those with the Cadence® Allegro® tools. Currently working with Samtec, he has previously worked for both Cadence and EMA, focusing on back-end PCB layout tool support. 

You come across an issue when using the tools, but you don’t understand why. Being able to troubleshoot an issue, and if needed provide a reproducible testcase to a peer or a Cadence AE, is the first step to resolving the issue.

If you have tried using Tools – Database check and that does not resolve the issue you will need to dig a bit deeper. When debugging the issue make sure it is reproducible. Also, are you on the latest release of the software? You can review the Readme_CCR.txt file to see if a similarly named issue has been resolved. This file can be found on the downloads.cadence.com site for the release that you are using.

Assessing whether this happens in all databases is one of the first steps to take. If needed, there are example databases which you can use for debugging or demonstrating an idea in the \share\pcb\examples\board_design directory of the install hierarchy.

If you can start the tools and see that the issue reproduces, you are well on your way to resolving the issue or helping a peer \ Cadence help you. You can note the steps taken to get to the issue or, even better, record a script that can be used to reproduce the issue. Open the drawing and select File – Script. Add a name for the script and then click Record.

Repeat the steps that show the issue and then stop the script by either clicking Stop in the Scripting dialog or enter stop at the command line. If you would like, you can add prompts to the drawing to describe what you are seeing. By typing at the layout editor command line, for example:

    confirm "Note how the clines spread too far."

Will produce this in the application:

When using this in a script, you will need to edit the script in a text editor to remove the fillin yes statement that follows your confirm statement or the layout editor will close the dialog.

When creating a testcase, leave only the layers that are affected enabled for display and zoom into the area of interest. While you may be intimately familiar with the issue and area of the design, a person that is seeing this for the first time would not be.

If the problem is a crash issue, you can use the journal file allegro.jrl and convert the journal into a script that can be used on the database. To best use this functionality, you should set the environment variable journal_nobuffer which is found in the file_management/journals category of User Preferences Editor before recording the script. Setting this variable changes the output of allegro.jrl to unbuffered. The advantage of unbuffered output is that sometimes with program crashes more lines are written to the journal file. I’d suggest only using this variable when you know you want to use allegro.jrl as a script, as it will slow the tool down.

To convert an allegro.jrl file into a script you can click Generate from the scripting dialog and browse to the allegro.jrl file or, you can open a command window in the directory that the journal file is stored and enter:

    j2script allegro.jrl textcase.scr

You may need to open the script file and remove the last few lines so the layout editor does not exit when replaying the script. Once you have a script that reproduces the problem, the next step would be to verify whether it’s a core tool issue or perhaps something in your environment that is the root cause. There are several methods you can use to perform this step which involves starting the tools without your environment variables.

One method is to rename your pcbenv directory. You can determine where your pcbenv directory is by opening a Windows file manager/Explorer window and at the top in the address line type:

    %home%

This will navigate to your HOME directory. Rename pcbenv to old_pcbenv. Restart the tools and none of your environment settings are used. Once you have finished with the debugging of the issue, you will need to delete the newly created pcbenv and rename old_pcbenv back to pcbenv to restore your environment.

The second method would be to open a command window where the drawing is located and type:

    allegro -safe

This will start the layout editor without any of your environment settings as if it’s was a fresh installation with no need to rename directories.

You then check to see if the issue will reproduce. If it does, you can be confident that others will be able to see the issue and provide a resolution or pass the issue onto Cadence engineering so that they can look into the issue.

What should be included when asking others to review a testcase?

The files below are needed when you are trying to show someone a problem you're having:

  1. The Allegro database, zoomed into the area of interest, with only those layers needed to see the issue enabled in the color dialog. If you are concerned with IP, use File – Export – Strip design… (strip_design command) to rename and/or delete items in the database.
  2. The allegro.jrl file.
  3. The variables for both the operating system (OS) and the layout editor:
    • To retrieve the OS variables, open a command window and type set >OS_env.txt. this will produce an OS_env.txt file.
    • To retrieve the layout editor variables, use the tool and select Tools – Utilities – Env variables. Save the results to a file named allegro_set.txt.
  4. Any files that are needed to support the layout editor tools. For example:
    • Artwork: photoplot.log, art_param.txt, and art_aper.txt (if applicable).
    • Import issue: any netlist files, DXF along with the conversion files, IDX, or IDF files.
  5. Any screenshots you would like to add. As they say, a picture is worth a thousand words. These can be added to a Word document that describes the issue if you need to provide text for context, or just included as the image files with reasonable names to tell what they show.

Making sure that the person you send the data to can see what you’re seeing gets you an answer much quicker, so taking the few minutes up front can save you hours of back-and-forth time later on when that person needs to come back to you with questions about how to reproduce your problem.

Rik Lee

BoardSurfers: Look Before You Leap - Verifying Footprints in the Design Capture Phase

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View the footprints of symbols during design entry in Capture: verify the footprint and land pattern dimension before exporting your design to a board layout tool, such as PCB Editor,(read more)
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