You can now leverage the 16.6-2015 release Allegro Rules Developer and Checker.

The Allegro Rules Developer and Checker allows you to develop custom fabrication and assembly rules to extend capabilities provided by Allegro PCB Designer and the Manufacturing Option. This tool provides a relational geometric verification language designed specifically for creating rules that are proprietary and custom to an original equipment manufacturer (OEM). The rules can be viewed and executed from the Allegro Constraint Manager, making it a single source for all design rules checks (DRCs) within a PCB.

There are two excellent videos that describe the details:

Allegro Relational Rules Checker: Running RAVEL Rules from Constraint Manager

Allegro Relational Rules Checker: How to Run DFM RAVEL Rules Through GUI

Please share your experiences using this technology.

Jerry “GenPart” Grzenia

The 16.6-2015 Allegro Design Workbench (ADW) release contains a significant enhancement that allows traditional Project Manager-based designs to use the same database enabled Component Browser used in ADW projects. Yes, the Component Browser can read the ADW database when editing projects in a Project Manager (non-ADW) flow.

Some designers want to stay in a Project Manager flow using parts from the ADW library database. Librarians use Allegro Library Workbench to build parts, but not all designers use Allegro Design Workbench. Until the 16.6-2015 release, engineers had to adopt the ADW Flow Manager (in Design Workbench) to access the ADW library. The Component Browser in a Project Manager flow could not see the ADW library.

In 16.6-2015, Project Manager flows can be configured to give the Component Browser access to the ADW library (an ADW license will be used). This provides:

• Faster part searches
• Quick Search capability
• Lifecycle and PPL data
• Shopping cart and lists
• Access to the richer ADW dataset on which to search and view
• Access to the component datasheet, using RMB on the part in the search results

The cds.lib file can point to both the local design and the ADW database, however local design cells can only be added in offline mode. Note that the ADW Library and Symbol Revision Manager (LRM/SRM) utility will not function in this mode and that non-PTF properties (those only included in the ADW database) cannot be extracted into a BOM.

Configuration is simple! In the project .cpm file, two entries are needed in a START_COMPBROWSER section: the ADW server URL and port, and a directive that enables or disables online mode:

This section can be controlled through a SITE level project template like any other .cpm file setting. It also works in Allegro FPGA System Planner.

Component Browser is now HotFix/ISR independent (this is only for clients used by design engineers – any update to the ADW server still requires an update to the clients used by librarians). Prior releases required the Cadence tools on the user’s machine and the ADW server to be at the same software revision (ISR). The ADW and SPB versions of the tools must still be compatible.

I look forward to your feedback!

Jerry “GenPart” Grzenia

The Allegro PCB Editor 16.6-2015 release now provides support for differential-pair return path vias, a method to add return path vias to a differential pair easily during the Add Connect command. Return path vias are also referred to as ground reference vias or stitching vias. They provide a current return path to minimize signal degradation in PCB and packaging interconnects by adding additional via(s), which are normally connected to ground, next to the diff pair via transitions.

The various capabilities include:

• Diff pair return path via setup
• Adding return path vias during Add Connect
• Working with diff pair and return path vias during Slide
• Defining via structures for use as return path vias

Diff Pair Return Path Via Settings

The return path vias functionality is available in the RMB context menu when a diff pair is selected for routing. After defining the return path net and via, you then will be able to select one of the six return path via styles to use when the diff pair is transitioning between layers.

Setup Tab

• Return Path Net: Select Net for the return path via. The menu contains a list of previously selected net names and the browse button will allow you to select a net name from the design. The dialog can be filtered by net name or by nets that have been assigned a voltage property (DC nets).
• Return Path Via (Padstacks): Select the padstack to be used as a return path via. The menu will contain a list of previously selected padstacks and the browse button will allow you to select a padstack from the design or library. The dialog can be filtered by padstack name or by the padstacks specified in the Physical Constraints Via list for the selected return path net (PCS net via list).
• Return Path Via (Via Structures): Select a pre-defined via structure to be used as a return path via. The menu will contain a list of previously selected via structures and the browse button will allow you to select via structure from the design. A stacked via structure can be created using Route –> Via Structure –> Define:

Spacing Tab—Define the Parameters for Each of the Six Return Path via Styles

• 1 Via: This style adds one return path via next to one of the diff pair vias. User has option to select Left or Right to specify which side of the diff pair to add to the return path via as well as the via spacing and angle. The default value for angle is set to 45 degrees for right, and 135 degrees for left.
• In line: This style adds two return path vias aligned in a straight line with the diff pair vias. User can specify return path via to diff pair via spacing.
• Equidistant: This style adds one return path via placed equidistant between the diff pair vias. User can specify return path via to diff pair via spacing. Enabling the Mirror option places one return path via equidistant between the diff pair vias on same side as diff pair pad entry routing.
• Offset: This style adds two return path vias offset with respect to the diff pair vias. User can specify the return path via to diff pair via spacing and angle. The default value for angle is set to 45 degrees.
• Diamond: This style adds two return path vias placed equidistant on each side of the diff pair vias. User can specify return path via to diff pair via spacing.
• Rectangular: This style adds four return path vias in a rectangular/square style centered on the diff pair vias. Users will need to specify x and y values in order to select this style for use.

Default value for spacing is set to Minimum DRC except for the rectangular style where the spacing defaults to 0. All entered user-defined values will be in database units and specifying different units is not supported:

Adding Return Path Vias During Add Connect

After the return path via setup is complete, you can enable one of the return path via styles from the RMB – Return Path Vias during diff pair routing. Enabled (check) return path via style to be used when routing diff pairs but changing the setting will not affect any previously added return path vias, which works similar to RMB – Via Pattern enabled settings:

Working with Diff Pair and Return Path Vias During Slide

You have the ability to slide the return path vias as a group, along with the diff pair transition vias, by selecting any one of the vias during the Slide command. It is sometime necessary to adjust the location of the either the return path vias or the diff pair transition vias, which can be accomplished by unchecking RMB – Return Path Vias Group. Once this RMB option is unchecked you will then see the RMB – Single trace mode when sliding a diff pair transition vias individually as normal:

Defining Via Structure for Return Path Vias (Allegro)

A via structure in Allegro is a series of blind/buried and/or micro vias stacked directly on top of each other that span multiple layers in a PCB. These via structures have traditionally been used in conjunction with the Create Fanout command (Route –> Create Fanout), which allows the attaching of the via structure (clines and vias) to the SMD pins of a device to complete the fanout (pin escape). Currently, defining a via structure in Allegro requires that the vias in the structure are physically connected to a pin, which in most cases means a cline is included when the via structure when created. For obvious reasons, these types of via structures should not be used as return path vias.

There is a simple solution: create a via structure that contains via objects only and no clines by placing the stacked vias inside the boundary of a SMD pad, then create the via structure using Route –> Via Structure –> Define:

A stacked via inside of SMD pin# 5 can be used to create a via structure for return path vias.

NOTE: These via structures will be exploded to their individual objects when they are used as a return path via but will remain as members of the return path vias group.

Limitations

• Return path vias
• Return path vias option is only available during Add Connect command
• Support is available for differential pairs only. Single-ended nets are not supported
• Multiple differential pair routing is not supported (i.e., Add connect of two or more differential pairs at a time)
• Using diamond and equidistant return path via styles will require a single click to set the gather point of the diff pair after/before it comes in contact with the return path vias
• Existing via structures that were created for use with the Create Fanout command may not be able to be used as return path vias as they normally contain cline objects
• Return path vias group
• Return path vias group is only available during the Slide command
• All vias that are part of the return path vias group will retain the associated net name when they were added, which is required to ensure that the return path net remains associated to the return path vias
• This results in a behavior change, compared to diff pair routing vias without return path vias. The diff pair transition vias will always retain the associated net name when they were added, even if the cline path back to a pin is deleted
• Even though the return path vias group is recognized by the Slide command, it is not possible to use other commands (i.e., Move, Copy, Delete, etc.) to perform actions on the group
• You have the ability to copy the individual objects that make up the return path via group but the copy will will not be recognized as a return path via group
• Expect the same bubble/smooth results during the slide of diff pair/return path vias compared to just diff pair transition vias only. If it is required to slide the group for long distances and in multiple directions, then it is recommended to delete and add them at the new location instead of using the Slide command

Please share your experiences using these new capabilities.

Jerry “GenPart” Grzenia

The current 16.6 HotFix now provides support for the Altium to Allegro PCB Editor Translator. The translator will convert both PCB and schematic files into Allegro PCB Editor and Allegro Design Entry HDL (DEHDL) files. Look to a future HotFix for the availability of the Altium to OrCAD Capture schematic translator.

Running the Altium to Allegro PCB Translator

In Allegro PCB Editor under the File menu select Import, Cad Translators, Altium PCB:

Note: A non-legacy PCB designer license must be used for the menu to appear:

 Browse to the ASCII PcbDoc Altium design file to be translated (see the note below on exporting the ASCII version of the Altium design):

When the “Create Individual Symbol Definitions” box is checked, the translator will generate a separate symbol definition for each instance of a component by adding a suffix. For example 0805_1, 0805_2, 0805_3 and so on. This allows you to account for instance-specific footprint modifications within in the Altium design. By default this option is unchecked, which means that the translator will create one symbol definition only for a given Altium footprint. Use this option only if instance-specific changes have been made in the Altium design.

Running the Altium to DEHDL Schematic Translator

In Allegro PCB Editor under the File menu, select Import, Cad Translators, Altium Schematic to DEHDL:

Browse to the ASCII PrjPCB Altium design file to be translated (see the note below on exporting the ASCII version of the Altium design). Then select the output project directory. By default, the translator tries to match the look of the original schematic. There are two options to control the graphics:

• Simple Symbol Graphic: Enabling this option will ignore any custom symbol colors defined in Altium
• Simple Symbol Pin: Enabling this option will ignore any custom pin shapes defined in Altium

Translating a Schematic and PCB Design Project

The process to translate an entire Altium project (schematic and PCB) is to first translate the schematic into DEHDL. Next, from the translated schematic, export an Allegro netlist into a new empty Allegro database. Then run the Altium to Allegro PCB translator from that Allegro database. Using this method ensures that the Altium2PCB translator will consider the netlist and device logic already imported and start to translate only the remaining data in order to complete the board.

Exporting the Altium Project to ASCII

To translate an Altium project, the Altium schematic and PCB database (.SchDoc & .PcbDoc) need to be in ASCII format, which is accessible under the file save data type in Altium:

Feel free to share your experiences using this new translator!

Jerry “GenPart” Grzenia

Documentation plays a significant role in helping to understand the software. Cadence is putting in lots of effort in developing different forms of documentation, from product manuals to videos, application notes, tutorials, Rapid Adoption Kits (RAKs), and point solutions. We are kicking off a new series to highlight interesting and useful content which gets added to Cadence Online Support.

Types of documents on Cadence Online Support

• Rapid Adoption Kits (RAKs) – RAKs help you learn the tool's features and flow quickly. RAKs usually consist of a working database and detailed manual to proceed and may contain a video.
• Application Notes
• Videos
• Troubleshooting Information – Point articles.
• Product Manuals

 Access these documents through the Resources menu.

• ·         Allegro Design Entry HDL
• ·         Allegro PCB Editor
• ·         Sigrity Power and Signal Integrity

The Allegro PCB Editor 16.6-2015 release provides Shape Edit Application Mode, a tuned editing environment optimized for the manipulation of shape boundaries.

In SPB16.0, all Allegro back-end tools with the exception of the PCB Router were enhanced to support a new pre-selection editing model; this involves the selection or hover-over of an element followed by command action. This model is commonly referred to as “Noun-Verb” in the industry. Hover-over data tips, context-sensitive RMB popup menu, automatic execution of commands with a LMB pick, and quick access to associated parameter options are attributes of the enhanced editing environment designed to maximize productivity in design canvas while reducing mouse travel to the toolbar or control panel. It’s important to note that there are commands available in Application modes such as Placement and Shape Edit that are not available in the legacy editing mode.

New functionality designed to improve the user’s experience editing shape boundaries includes:

• The sliding of shape edges with or without corners
• Corner conversion
• Multi-segment sliding and the adding of notches

When entering the Shape Edit App Mode, note the Option Panel supports command options that accelerate the editing of the boundary. A LMB click or Drag is the recommended method to perform the essential shape edit functions:

Sliding a Segment (Shape Edge)

Hover over the right side shape edge as shown below. Your datatip may look different than what is displayed. Use the Tab key to cycle between the “segment” and “shape” element. After pressing the Tab key a few times, finalize with the “vertical line segment” being highlighted as shown below:

While hovering over the highlighted line segment, use the RMB to access the Slide Segment command. Slide the segment towards the right, then make a LMB pick in black space to clear the selection buffer.

Next we use an accelerated method to perform the same function. Refer to the Options Panel and note the settings for “Click” and “Drag”. With ‘Drag” currently set to “Slide”, hover over the same shape segment, then depress your LMB to slide it:

Change the “Click” value from Add Notch to Slide. Simply make a LMB pick on the segment to slide it. Similar behavior in Etch Edit Application mode for sliding segments.

Perform any of the above steps on a Circular shape:

Extended Segment Slide

Enable the option “Extend Selection”. You can also use the SHIFT key to toggle the state of the “Extend Selection” option if you prefer:

Select the straight section of the shape edge as shown below. Ensure the segment is highlighted as you begin to hover over it, then slide it, noting how the corners are maintained during the dynamics:

Disable the “Extend Selection” option and slide the segment, noting the behavior is limited to just the single segment:

Perform the same steps to slide the edge of the rounded rectangle that is located to the right of the chamfered rectangle:

Adding a Notch

Adding a notch is a two-step process where you select two points on a straight segment and extend inward or outward. The example below is an “inward” notch:

Hover over the bottom segment, then use the RMB to access the Add Notch command. Position the two white squares that define the notch width, then move your cursor to define the notch length:

Use “single-click execution” mode to add the next notch. Ensure the “Click” option is set to “Add Notch”. Based on the figures below, make your first LMB pick, then use RMB – Snap Pick to – Segment Vertex to add the second pick directly at the corner vertex location:

Add one more notch using the RMB – Add Notch method. Hover over the inside segment as shown in the left figure below, then use RMB - Snap Pick to – Segment Midpoint to place the first point at the midpoint of the segment. Add the second notch at the corner using RMB – Snap Pick to – Segment Vertex:

Move Vertex

Selecting a vertex location on a shape boundary performs a two-segment move. Hover over the lower right corner of the shape, you will notice the change in style of the cursor. Use the RMB to access the Move Vertex command. Move your cursor to increase the shape width and length:

Perform the same action using a single LMB click or DRAG based on the “Vertex commands” setting shown below. Click on one of the inside boundaries of the notched shape and extend upwards and also to the right:

Chamfering Corners

Adjust the settings as shown in the figure below. Hover over the top left corner then use the RMB to access the Trim Vertex command. Referring to the bitmap “T”, a value of 25 produces a 35.36 chamfered length - [Square root of (25 squared + 25 squared)] = 35.36:

Change the setting from Trim (T) to Chamfer (C) and use the same 25 value. Make a single LMB pick on another 90-degree corner. The length of the chamfer should be 25mil, as shown in the right image below:

Enable the setting Set trim size by cursor:

Select another vertex location and adjust the chamfer by moving your cursor:

Rounding Corners

Adjust the settings as shown in the figure below, with corners now set to “round”. Disable the setting “Set trim size by cursor”:

Hover over a corner vertex location then use RMB – Trim Vertex:

Change the setting to Radius (R) = 25:

Make a LMB pick on another 90-degree corner to create a 25mil radius, continue changing corner types as you please. Round the upper route corner of the route keepout shape:

Chamfering All Corners

Adjust settings as shown in the figure below:

Hover over a line segment associated with the shape, then RMB – Shape – Trim vertices:

Rounding All Corners

Adjust the settings as shown below:

Hover over the shape boundary, then use Tab key to ensure “shape outline” is active. Note the datatip display of “Dynamic Shape Boundary”:

While hovering over the boundary, use the RMB to access the Trim vertices command. This is the second command in the list:

Joining Segments

Adjust settings as shown in the figure below. Select the upper right vertical segment and slide to the left noting the behavior. Undo or Oops to revert back to original shape:

To join the segments, enable the Auto-Join setting as shown below. You can also use the CONTROL key to toggle the state of the setting:

Select the same vertical segment and slide to the left, noting the joining behavior with the adjacent segments. If you experience an issue performing this step, click the Tab key to ensure you are acting on a segment and not the shape boundary. This should be the final result of your editing:

Sliding Multiple Segments

The goal of this step is the slide the entire right edge to the right while maintaining existing segment construction:

Select the three vertical segments on the right side of the shape. You can do this by depressing the SHIFT key, then make three individual selections. Hover over any one segment then use the RMB to access the Move Segments command:

Move the group of segments to the right.

I look forward to your comments!

Jerry “GenPart” Grzenia

The 16.6-2015 PSpice release has several new features and capabilities:

VBIC Support Added in PSpice

In case of early effect, quasi-saturation, temperature modeling, avalanche multiplication, and so on, VBIC, a bipolar junction transistor (BJT) model, can be used instead of the SPICE Gummel-Poon (SGP) model for better modeling than SGP.

Beginning with the 16.6-2015 release, a new Q device, which is a npn-type BJT model, is added to Capture library for the Capture-PSpice flow and can be accessed from breakout.olb. The model definition and netlist instance of the QVBICN model are:

• Model Defination: .model QVBICN CMI VBIC npn=1
• Netlist instance: Y_Q1 C B E S CMI orPSpiceDevices.dll QVIBICN

QVBICN is an example of Device Model Interface (DMI) support that is used to create specific devices from the model DLL files:

Note: The following PSpice DMI models require an Allegro AMS Simulator license for simulation:

• Digital and SystemC DMI models, such as Digital LogicExp devices using CMODEL parameter
• Analog DMI models, such as Y devices
• Models translated from VerilogA-ADMS

The DMI models that are shipped with PSpice, such as QVBICN DMI model, do not require the Allegro AMS Simulator license.

New Device Added in PSpice for DMI Support

A new generic device, Y device, is added in PSpice for DMI support. Using this generic device and DLL files, you can create various type of devices, such as BJT, voltage-controlled voltage source (VCVS), and thin-film transistor (TFT).

The DLL files are generated by compiling the C code. You can modify the C code to generate a device that can perform a specific function.

For more information on DMI models, refer the Device Model Interface section in PSpice A/D Reference Guide.

For more information on generating DLL files and compiling C code, refer to the following documents:

• PSpice DMI API Reference Guide
• PSpice Device and System Modeling with C/C++ and SystemC

ADMS XML Filters for Verilog-A to PSpice DMI Models Translation

Beginning with the 16.6-2015 release, Verilog-A models can be simulated by PSpice when converted to PSpice DMI models. The Verilog-A models are converted to an equivalent-C code by Automatic Device Model Synthesizer (ADMS) using the PSpice DMI-compatible XML filters, which are located at <installation>\tools\pspice\api\adms\xmls. The generated C code can be compiled into PSpice DMI-compatible DLL files.

For more information on Verilog-A support in PSpice, refer the PSpice Device and System Modeling with C/C++ and SystemC document.

Note: Only the ADMS-supported Verilog- A models are converted to PSpice DMI models.

Documentation Enhancements

Two new documents have been added for DMI support in the <installation>\doc folder:

• PSpice Device Modeling Interface API Reference Guide: Describes the APIs that can be used to generate and compile the PSpice DMI DLL files
• PSpice Device and System Modeling with C/C++ and SystemC: Provides step-by-step instructions for generating and compiling new SystemC DLL files

PSpice Lite License String Added for PSpice Lite Mode

Before 16.6-2015, there was no option to launch PSpice in Lite mode if you had any valid license. Now you can use the new license string, OrCAD Lite - PSpice, to launch PSpice in the Lite mode, even if you have a valid license:

Note: You cannot switch between the Lite and the licensed version of PSPice in the same session. You have to restart PSpice and select the required option.

I’m looking forward to your feedback!

Jerry “GenPart” Grzenia

Several new features have been added to the 16.6-2015 SiP release.

Read on for more details …

Co-Design Die Editing in Symbol Edit Application Mode

The Symbol Edit Application Mode has been expanded to operate on co-design dies as well. A co-design die is one that was created by the loading of a die abstract. Using the Symbol Edit Application mode, you can refresh a co-design die symbol and also view and edit die bumps and I/O drivers:


Using the new options, you can easily balance the ideal bump pattern with respect to both the drivers and top level metal in the IC and the pin escape pattern on the package substrate, or bond wire pattern for a bonded die; for example, you can optimize the bump pattern with respect to both the drivers and the package pins or optimize net assignments.

Use the Refresh co-design die option to refresh a die in the database from the disk file or to make a library change.

After displaying the I/O drivers of a co-design die using Show IC Details, you can perform the following operations on the selected drivers:

•      Move
•      Align
•      Respace
•      Swap
•      Change Driver Placement Status

Defining Variants

You can now define subsets of components and cross-section layers in a master design so that each subset is a single variant of that package design (Manufacture - Define Variants). For example, you might define two variations of a memory stacked design, where each variant has memory chips from a different set of vendors. Using the variants feature, you can create a master design that contains the dies for the different variants, and then define a variant for each set of dies which will be assembled together in a final, packaged substrate.


This feature saves design time by allowing you to design once, and then analyze and manufacture many times; you manage all physical connections in a master design and then generate variant designs that are ready for SI and PI analyses, 3D DRCs, and documentation generation.

By using the variants feature, you ensure that when the package substrate is updated, all the variants are updated; decreasing the chances of synchronization and manufacturing or assembly errors. For example, when pushing and shoving a bond finger in the master drawing, all bond wires connecting from any of the variants' dies are updated at the same time. Similarly, if a new finger is added such as a blank bonding target in some variants, the finger label of all variants are updated and geometries exposed through soldermask openings are kept in sync. The overall impact is a greatly reduced probability of errors during manufacturing or assembly of any of the final packaged components.

Replacing Via with Via Structure

You can now create as detailed a via pattern as necessary in an efficient, quicker way while performing interactive routing. Use the new replace via with via structure command to replace selected or all vias that use a specific padstack definition with instances of an existing via structure definition. For example, use a large via, which reserves the space needed for a more complex via structure pattern, during initial routing. When routing is complete, replace the placeholder via with the via structure to create the final, detailed routing.

You can also use this command to replace instances of a via structure with a via in order to restore the design to its original state with the original vias.

Changing Symbol Owner

You can now interactively add static shapes as children of a symbol instance. For example, you can add texts, fiducial vias, alignment lines, or reference outlines or shapes. Any operation, such as move or delete, performed on the parent symbol instance will also occur on the children.

Note: If you refresh a symbol from library, any instance items will be be deleted. If you want the instance items to be preserved, disassociate the instance items first and then reattach them after refresh.

Use the change sym owner command either to add database objects as children of a specified symbol instance or to remove current children from their owning parent symbol instance.

Exporting Netlists

You can use the netlist spreadsheet command to export a spreadsheet style netlist to be used for documentation purposes. The spreadsheet is organized as a set of columns for each component: any BGA components, followed by die components, and, finally, discrete components. The cells are colored according to the color of the nets in the design. The spreadsheet contains columns for Net name, RefDes, Pin Number, and Pin Name.

Degassing Enhancement of Void Clearance for Adjacent Layer Shapes

You can now specify the behavior of degassing void creation depending on overlap with adjacent layer shapes using the new Adj. layer void clearance option. Earlier, shapes on adjacent layers were ignored by degassing. Now, in addition to the default behavior that ignores adjacent layers, you can also specify the following behavior by selecting the appropriate option:

•      Inside Shape: Degassing voids will only be created if the void is entirely inside an adjacent layer plane shape.
•      No Void Overlap: Degassing voids will not be created if there is an overlap with a void in another shape.

Please share your experiences using these new capabilities.

Jerry “GenPart” Grzenia

Cadence Online Support Features

“Most Popular”:  This section displays content items basis your “search” and technology platform selections.

Use My Support - What's New to explore the new features of Cadence Online Support (COS).

Product Manuals
You can access product manuals for all the supported releases. Have you checked out Sigrity 2016 document yet? If not, click here …

 
A wide variety of informative content has been published on COS. Check it out–

Application Notes

Installation and Licensing

The 16.6-2015 RF PCB release contains many new features and updates. Read on for more details …

Allegro Discrete Library to ADS Translator Enhancements

This release includes several enhancements in Allegro Discrete Library to ADS translator. The following image illustrates the latest UI of the tool:


Support for Schematic Symbol Version
You can now define versions for a schematic symbols in the CSV file. On loading a CSV file, a new column is added to the Selected Parts grid. Only those symbols for which a version is defined are translated.

Filter Support for Searching a Library or Part
A filter field is added to search for library part(s).

Associate Selection of Part with Selected Parts Grid
For the parts displayed in the Selected Parts grid, the corresponding libraries are enabled in the tree view.

Support to Select/Unselect All Parts
When the Select/Unselect all check box is selected, all the library parts are added for translation and displayed in the Selected Parts grid. Similarly, disabling this checkbox clears all the selected libraries from the Selected Parts grid.

Performance Improvement
The response time of translator GUI is reduced. The translator no longer parses all the libraries to display the GUI, and improves the performance as a result.

Non-Graphical Mode for Batch Translator
The batch command is enhanced to run the translator in a non-graphical mode using a new option, -auto. This option suppress all graphical user interfaces including the splash window, translator main dialog, and progress window.

Preserve Casing of a Layer Name in the Mapping Process
The mapping process of the translator now preserves the casing of the layer name in ADS and also displays the layer name in the Edit Layer Map dialog:

IFF Import and Export Enhancements

The RF IFF Import and RF IFF Export commands are enhanced to support the editing of layer map files. You can edit the current layer mapping settings using a text editor and save them in a text file.

RF IFF Import
New options are provided in the RF IFF Import to export and import layer mapping settings:


For more information, see Allegro PCB Editor to ADS (Export IFF) in Allegro User Guide: Working with RF PCB.

RF IFF Export
In RF IFF Export interface, the layer mapping settings can be edited by enabling a new option, Layer map new mode in the More Options dialog. The RF IFF Layer Map dialog presents options for importing, editing, and restoring the current layer mappings:

For more information, see ADS to Allegro PCB Editor (Import IFF) in Allegro User Guide: Working with RF PCB.

Manual Placement Command

In 16.6-2015, a new rf_manualplace command is added to support the functions of placing components that are not available with the existing autoplace command:


Using the Manualplacecommand you can interactively place revised or unplaced components in the design. You can also select multiple components and place or update them sequentially. This command lets you easily check the schematic changes after the netlist is re-imported. On selecting a component, the cursor dynamics changes and show the outline of the component. Before placing the component you can select a pin to fix for the autoshoving:


While placing or updating a component, you can perform the following actions:

•      rotate the component
•      skip the current component and select next component from the list
•      select start pin
•      snap to the pad edge of etch object or any other component
•      create clearance assembly or merge into existing assembly of surrounding objects
•      auto-shove of placed objects that are connected to the component

Miscellaneous Enhancements

Cross-probing between DE-HDL and PCB Editor

When you edit an RF design and select an RF component or its pins in Design Entry HDL, the corresponding pins of the component are selected in PCB Editor.
The cross-probing between Design Entry HDL and PCB Editor works only if they are launched from Project Manager.
On cross-probing an RF component or its pin, rf_manualplace command becomes active in PCB Editor and lets you place or update the component:



Support for Rotation-Pick Mode in Placement Commands
In this release, the component placement commands support a new rotation-pick mode. In this mode, you can rotate the component before picking a destination.This mode is available for the following commands:
     rf_autoplace
     rf_manualplace
     rf_add_component

You can start the rotation-pick flow using the new right-click pop-up menu, Rotate. The following figure shows the updated right-click menu for rf_autoplace, rf_manualplace, and rf_add_component commands, respectively:


I look forward to your feedback.

Jerry “GenPart” Grzenia

Significant enhancements to the 16.6-2015 Constraint Manager release have been made in the following areas:

•      Tag-based ECSet Mapping
•      Single-Step Method for Creating Class-Class Relationships
•      PCSets and SCSets Difference Reports

Read on for more details ...

Tag-based ECSet Mapping
The process of applying an ECSet to target nets involves mapping the pins in the ECSet to the component pins in design for those nets. This process looks at many factors including signal_model assignments, pinuse, and RefDes to make a match. Difficulties can arise when the mapping is forced to rely solely on RefDes information and there is no one-to-one correlation between the RefDes information in the ECSet and the design. Take, for example, the following topology:

The mapping process has no way to distinguish between U2, U3, U4, and U5 except by RefDes. To address these issues, ECSet nodes now support tags (pin parameter) which can be used to uniquely identify a pin and remove any ambiguity. This can be used to lock the mapping between the ECSet and associated nets and will not be impacted by placement or RefDes changes.Tags can be defined in a design prior to ECSet extraction or ECSet application and can also be defined in SigXplorer.

Tags driven from SigXplorer
When the Update Constraint Manager command is executed, the following dialog is displayed:


Tags can be added in SigXplorer to the specified nodes using the Parameters pane:



When the ECSet is applied to target nets, an interactive dialog is displayed where you assign the tags in the ECSet to the appropriate pins in the design:


This dialog shows the original log file at the bottom with new messages for cases where the ECSet has mapping tags but the design does not. The top portion contains pulldowns in the (X)Net section to use the Pin column or the Tag column to map the appropriate tags to the proper pins, and then update all the applicable objects which reference the same ECSet.

Tags Driven from Design
Tags can be added to pins in a design prior to extracting a topology into SigXplorer. The tags can be used to schedule a topology and when the topology is applied back to the design.
ECSet mapping tags are also supported in the front-to-back flow between Design Entry HDL and Allegro PCB Editor.
For more information see the Mapping ECSets to Nets Using Tags in Allegro Constraint Manager User Guide.

Single-Step Method for Creating Class-Class Relationships
This release includes a usability enhancement to ease the process of creating and updating class-class relationships between Net Classes and Region Classes in the Spacing domain.
When you select the Constraint Set References command for a design, or a Region, a dialog displays a matrix of Net Classes. By clicking a cell, you can create Class-Class relationship between two Net/Region Classes and also apply an SCSet available from the drop-down list:


This solution works only if spacing CSets, Net Classes, and Region Classes are already in the design.
For more information, see Objects - Constraint Set References in Allegro Constraint Manager Reference Guide.

PCSets and SCSets Difference Reports
In this release, Constraint Manager is enhanced to provide support for comparing physical or spacing constraint sets. When a constraint set is selected, a new option Compare appears in the pop-up menu. On selecting a single constraint set, a Select Object dialog is displayed where you can select a constraint set to compare:

On comparing two CSets, an XML-based report is generated that opens in the built-in browser:



I welcome your feedback!

Jerry “GenPart” Grzenia

The 16.6-2015 Design Entry HDL (DEHDL) release contains a few new capabilities!

Read on for more details…

Read-only Sheet Import
In Design Entry HDL (DEHDL), the sheet import command now supports the import of schematic sheets in read-only mode. For details, see the Importing Designs section in Allegro Design Entry HDL User Guide.

Component Browser - ADW Mode
You can now access the Component Browser in two modes--the standard mode and the Allegro Design Workbench (ADW) mode. The ADW mode allows you access to a larger, and accessible-from-anywhere dataset, of components.

The ADW mode (also referred to as the online mode in the documentation), enables faster, free-text searches, provides life cycle functionality, preferred parts lists, alternate manufacture lists, and provides a shopping cart that allows you to search for parts that are selected or added to a design.

For more information, refer to the Using Component Browser section in Allegro Design Entry HDL User Guide.

Tag-based ECSet Mapping
User-defined tags in ECSets can be added to pins or components in a design prior to extracting a topology in SigXplorer. These tags can be used to schedule a topology and are used when the topology is applied back to the design.

ECSet mapping tags are also supported in the front-to-back flow between Design Entry HDL and PCB Editor.

For more information, refer to the Working with ECSet Tags section in Allegro Design Entry HDL - Constraint Manager User Guide.


Please share your experience using these new features.

Jerry “GenPart” Grzenia

Cadence Online Support Features

Setting up ‘My Alerts”

 
The My Alerts section displays a count of the new content items added.  This is generated taking into account your notification, search and technology platform selections.

You can click the link to view the list of new content in a search results page.

Use My Support - What's New to explore the new features of Cadence Online Support (COS).

Sigrity 2016

A central page is created which host all the important links to Sigrity 2016 documents. Check out the “one stop shop” for Sigrity 2016 content

Vidoes

Application Note

RAKs

Leave a comment below or make use of the Feedback mechanism within Cadence Online Support.
Hope you find these knowledge resources useful.

~Jasmine

With the Allegro Design Workbench (ADW) 16.6-2015 release, you’ll have several new capabilities that enhance your productivity.

Read on for more details …

ADW Server Error Logging and Notification

The ADW Server can log the errors, warnings, and information messages and report them through e-mails. These messages enable the administrator to monitor the health of the server, and take the necessary corrective action. These messages are logged in the <adw166>\pcbdw_lib\server\log\adwserver.out file. You can also configure the server to be notified through e-mails.

Monitoring the health of the ADW server should decrease admin response time and increase server uptime. More than 70 server messages have been clarified and enriched. Messages are labeled as Error / Warning / Information. Email is configured on the ADW server through a logging.xml file

For detailed information, see the Allegro Design Workbench Configuration Guide.

Enhancements in Classification Revision

The classification revision process creates a new version of the classification, and processes the Development Status of associated parts and models on the basis of the options you select in the Revise message. If, however, the revision is not successful, you need to right-click the newly created classification node with errors and choose Continue Revision:


For detailed information, see the Allegro Design Workbench Database Editor User Guide.

Enhancements in Library Import

The Pre-Analysis Report contains the result of running the pre-analyze tool of Library Import. This report has been enhanced to ensure that each section of this report provides detailed description of the errors, warnings, or information found during pre-analysis. It also gives information on how to correct the errors. You need to review all the reported errors and correct them before importing the libraries into the ADW Component Database.

The goal is to shorten library import time by providing clearer, more robust, more thorough feedback. Issues reported by pre-analysis are now classified as Error / Warning / Information. All errors must be resolved before import can proceed. The pre-analysis report has been redefined:

• Structured report for easier readability
• Issues are grouped according to type of issue
• Consequences of not resolving the issue are clearly described
• Report is sorted, where appropriate

The support to handle the temporary libraries has also been enhanced. With this release, you will not be allowed to choose system created temporary libraries while creating an object. You cannot create a library with the same name as any temporary library. During library import, there might be cases where the key and injected properties have the same names but different values in the PTF files of the source libraries selected for import. In such cases of duplicate properties, you can choose which property value should be added to the ADW component database:

• Both properties    
• Only key property
• Only injected property

For more information, see the Allegro Design Workbench Library Import Guide.

Condensed Library Flow
In addition to the existing standard library flow, ADW now has a condensed flow for creating, validating, and distributing models. In this flow, each model type, the New and ECO subflows have been combined into a single flow. It also enables easier import of models created by the third-party vendors.

For details on this flow, see the Allegro Design Workbench Flow Manager User Guide.


Please share your experience using these new capabilities.

Jerry “GenPart” Grzenia

This year’s CDNLive Silicon Valley developer conference had more than 125 presentations from 12 different technical tracks. More than 25 exhibitors participated in the Designer Expo.

The IC Packaging/Signal Integrity/Power Integrity track featured customer papers on co-design as well as signal, power, and thermal integrity. With the challenge of creating final products as quickly and as efficiently as possible, two papers stood out as audience favorites. It is no surprise that each of these papers utilized a number of Sigrity™ tools in the methodology, but ultimately utilized Sigrity SystemSI™ technology to ensure the product was working to industry compliance standards.

The first user paper highlighting SystemSI technology was presented by Ken Wu of Google. Ken showed the audience one of the latest Google Chromebooks and discussed the challenge of USB Type-C connectors and the multi-gigabit USB SuperSpeed interface design. Ken walked through both pre-layout analysis and post-route analysis and using Sigrity technology to check compliance of the interface.

To review and download Ken Wu’s paper, click the image below.

Another user paper highlighting use of Sigrity technology was delivered by Alex Tain of Seagate. He discussed methodologies used in creating Seagate solutions utilizing Flash technology.

Alex reviewed his design and analysis methodology, which includes using Allegro implementation tools for the PCB and IC package design. The methodology also utilizes Sigrity tools for analysis, interconnect extraction, and interface compliance testing.

To see Alex’s paper and how Seagate performs Flash memory interface simulations, click on the image below.

Thanks to Ken Wu, Alex Tain, and all the other contributors to CDNLive SV 2016. It was a lively and highly educational conference.

Team Allegro

Cadence Online Support Features 

"You might also be interested in” Section

“You might also be interested in” section in Cadence Online Support (COS) section is present immediately under the document being displayed.

This provides links to additional material that might be of interest to you. The links are generated dynamically on the basis of the current document being read.

Rapid Adoption Kit (RAK)

Constraint Manager Xnet Setup and Configuration
This document guides you through the basic process of setting up Xnets in a High-Speed design. The scope of this document is the setup of Xnets and is not a full design simulation scenario.. This document guides you through the basic process of setting.

PCB Editor - STEP Model Tutorial
This document outlines the processes and procedures required to setup and use STEP models inside Allegro PCB Editor. It covers:

• STEP Model Support in PCB Editor
• Mapping STEP Models in the Symbol Editor
• STEP Model Mapping in PCB Editor
• Mapping Mechanical STEP Models
• Mapping a Mechanical STEP Model to a Board Drawing

Application Notes:

How to Visually Compare Layers From One SiP Design to Another?
At times you need to compare a layer of one SiP design with a layer of another design to compare the metal differences. For example, there could be variant designs where  routing is slightly different to achieve specific impedance, inductance, resistances, or capacitance. By using the Batch Layer Compare feature, you can identify these differences.

Packaging Synchronization Checks for Reuse Blocks in Design Entry HDL
This application note describes new DE HDL checks introduced to address and verify synchronization status of reuse block schematics and the packager (PXL) block state files when working in a team based hierarchical environment.

DML Library Reference and Management
The purpose of this application note is to review and inform users of features available to them when trying to manage their local DML libraries.. The purpose of this application note is to review and inform users of features available to them when trying to manage

Front-to-Back System Co-Design Flow Guidelines
This application note provides system design flow guidelines for a team of designers. The goal is to establish a scalable, error-free, design-flow methodology that allows for concurrent system design development (schematic, board, and constraints) while maintaining design data integrity and synchronicity.

Videos

PDN Capacitor Additions for What-if Analysis in PowerSI
This video shows how to add capacitors to a PDN layout to perform what-if analysis in PowerSI.

Analyzing a Decap Configuration in the Allegro Sigrity PI Power Feasibiltiy Editor
The first order single node analysis in the Power Feasibility Editor makes it very easy to evaluate the usefulness of you decoupling capacitor scheme and try a variety of different scenarios..

Adding Termination in SystemExplorer
This video shows how to add terminations to a SystemExplorer simulation..

Training Bytes:

Self-learning videos to learn more on the tools can be seen from Training Bytes. New videos have been published for:
Allegro Design Entry HDL
Allegro PCB Editor
Sigrity Power and Signal Integrity

Leave a comment below or make use of the Feedback mechanism within Cadence Online Support.
Hope you find these knowledge resources useful.

Jasmine

With the 16.6-2015 Allegro PCB Editor release, the Snake pattern router can be enabled from the context menu of the Add Connect command. This functionality provides the ability to route through hex pattern packages utilizing arc routing, which has been greatly improved compared to the existing prototype pattern generator. Simply enable Snake mode via the RMB and Add Connect will detect a hex pattern pin/via field and dynamically convert to arc routing:

 

Read on for more details …
 
Snake Mode and Options
The Snake functionality is available in the RMB context menu after selecting a net for routing using Add Connect. Once in Snake mode the bubble options under the Option window will be automatically disabled as the route will be dynamically weaved through the hex pattern as you move your cursor through the pin/via field. Selecting a point outside of the pin/via will convert back to standard line mode to continue routing and convert to arc routing once re-entering the pin/via field. This will allow easy transition from arc to non-arc routing when voids exist in the pin pattern:

     
•    RMB – Snake options – Center Single Traces in Channel

 
This option setting will automatically center the route in the center of the channel and as you move through the channel, it will dynamically show what the resulting route will look like. Clicking with the LMB will accept the pattern as you see it:

 
•    RMB – Snake options – Switch Single Trace to other Lane

 
When the Center Single Traces in Channel is not enabled, you have the ability to switch between the nearest or farthest channel for dynamic routing using Switch Single Trace to other Lane:

 
Routing behavior during Add Connect
Once Snake mode is enabled, Add Connect will detect a hex pattern pin/via field and automatically switch over to arc routing, allowing two single routes or differential pair routing in the channel. Starting a single connection will default to the nearest channel, reserving space for an additional trace in the opposite channel using the default same net spacing. As you move your cursor through the pin/via field, it will dynamically show the resulting trace.

Route a single trace in nearest channel:

 
LMB Select the opposite channel and route a single trace in the farthest channel:


Indicating in a direction will dynamically show the expected route path:

        
LMB Select to guide the dynamic route in the route direction:

       
NOTE: LMB Select outside of the hex pattern package pin field will convert back to normal (non-arc) routing, and re-entering the pin field will convert back to arc routing with Snake mode enabled.

Limitations
•    Single route, two routes, or a single differential pair route will be equally spaced in between the pins/vias in the channel. If the constraints do not allow two between routing, you will see traces dynamically highlight, indicating that a DRC error condition exists and an LMB Select to commit the dynamic routes will result in DRCs.
•    Bubble and Smooth options are disabled when Snake mode is enabled.  
•    Routing in an offset channel (single trace) and switching to a center channel route using RMB – Snake options – Center Single Traces in Channel will produce a 90-degree corner at the transition. Improved transition is expected in 17.2.
•    Snake pattern routing will be disabled once an LMB Select is made outside of the pin field and convert back to Snake pattern upon entering the pin field again. To get a predictable bubble result outside of the hex pattern package, we recommend disabling Snake mode.

Some performance impacts have been seen when the routed cline contains a large amount of arc segments or when excessive arc weaving is done inside of the hex pattern package.

Looking forward to your input!

Jerry "GenPart" Grzenia