Beginning with the 16.6 version of Allegro PCB Editor, you can now toggle the Analysis flag directly from the Constraint Manager (CM) column header without using the “Analysis Modes” dialog.

Read on for more details …

The Constraint Manager column’s header is colored in yellow in case the related Analysis is set to OFF.
Here is a screenshot from the Electrical Worksheet > Net > Routing > Wiring:

 
In the Analysis mode you will see that the related DRC modes are OFF:

 

Click the right mouse button on a column header and select the Analysis Modes menu item:

 
Selecting Analysis Mode will set the related Analysis to ON and the header color will not display it as yellow:

 

Please share your experiences using this new capability.

Jerry “GenPart” Grzenia

You’ve no doubt seen announcements (either via customer emails, on the Cadence website, on the Cadence Customer Support portal, etc.) about Quarterly Incremental Releases (QiRs). QiRs have been made available for over a year now with a focus on updates to the 16.6 release.

In case you’re not familiar with QiRs, they are an exciting new way of bringing Cadence users valuable new features without having to wait for 12 to 18 months for a huge new software release. QiRs simply install on top of your current latest release, and they do not affect quality, stability, or methodology. What they do bring are a host of new capabilities, most of which will improve your designer’s capabilities and productivity. Imagine not having to load and digest an entire new release just to get access to cool new capabilities and productivity features! To get the latest QiR:

1. Navigate to the main Cadence website and then to the PCB Design section.
2. From this page, on lower right, you’ll see a link “Allegro 16.6 Quarterly Incremental Report”. Select this and see the current QiR4 content.
3. Navigate to the Allegro Software download page and download the latest QiR.

I have already blogged about several new features available in the 16.6  QiR1 to QiR4 downloads and will continue to post blogs about new QiR features over the coming months.

If you’d like to see all the great new features and capabilities in prior QiR releases, simply type “QiR 4” (or “QiR 3”, or “QiR 2”, etc.) in Cadence Online Support and you’ll get all the details:

 


You can also access the details from any of the product Help Menus (Help > Documentation > Release Info tab and then the link “What's New in Release”.


Look for Allegro Team blogs soon after the QiR5 becomes available!

Jerry “GenPart” Grzenia

Recently, an article was published in Printed Circuit Design and Fab by Cadence product manager Kevin Rinebold talking about Multi-Fabric Planning for Efficient PCB Design(see page 22 of printed magazine).

Today's BGA-style packages have a significant impact on PCB layer count, route complexity, and cost. Efficient BGA net assignment and patterning of power and ground pins can make the difference between a four- and a six-layer PCB. Historically, there's been minimal visibility or consideration of the PCB during package net list development, which itself is a direct function of the I/O pad ring layout of the chip. In addition to the layer count and cost, performance margins of high-speed, high-bandwidth interfaces can no longer accommodate poor pin assignments and overly complex routing schemes.  The good news is there are new methodologies and tools that enable the necessary coordination and multi-fabric visibility to properly plan and manage these challenges.

The article presents a methodology for PCB-influenced die/package planning of cross-fabric interfaces showing the relationship to PCB layer count and complexity. It explores the relationship between the I/O pad ring, die bumps, package ball pads, and critical devices on the PCB. It discusses techniques to optimize connectivity across these elements along with the role of route feasibility to validate pin assignments. Routing tools and methods to address the complexity of high-performance interfaces like DDR4 or PCIe 3.0 are also covered at both the package and PCB level. Finally, the article touches upon data exchange and communicating design intent when working with external resources or geographically diverse design teams.

Read the full article and tell us about your experiences of using multi-fabric planning methodology!

Team Allegro

• All net instances contain Cross References only for net instances connected to primitives
• Net instances connected to a block symbol will not be included in the Cross Reference list
• Net instances connected to a block symbol will contain the list of all net instances connected to primitives

1. Only a single designer can work on the physical view of the design at one time
2. Multiple physical designers can work concurrently
   • Multiple board files can be managed independently under the physical view
   • Board files can be assigned to different users (the Physical Design Integrator assigns users to board files)
   • Users check-in and check-out board files from the TDO dashboard

While there are several videos available for Allegro Design Entry HDL (DEHDL) in Cadence Online Support as well as in the product installation documentation folder ($CDSROOT/doc), there are times when a new specific video is produced for product features. Of course, there are many videos available for all the SPB products. Recently, several new videos have been produced for some of the more common functionality areas of DEHDL. These videos can be utilized by design engineers who would like a quick refresher on the best practices/recommended techniques to use.

Read on for more details…

As you may recall, it’s easy to quickly find product videos on Cadence Online Support. Simply navigate to http://support.cadence.com and at the top links section, choose Resources > Video Library. In this next screen, depending upon the products you’ve filtered in the “my preferences” section,  you will see the most recent videos posted:


If you click on the  “View all content for my products:” link at the bottom, you will see all the available videos.

One of our most expert application engineers - Henk Van Haaren – has taken care to provide you with not only the details of specific product and flow capabilities in a PowerPoint format (for quick reference), but also a demonstration on how the feature works! He has developed 12 videos which can be viewed in a quick 10 minutes or so. The content reflects the most efficient usage methods that Henk has dicussed with many customers over the years.

Here’s the complete list:

• Working with Bottom Up Hierarchy
• Working with Top Down Hierarchy
• Creating Reuse Block 
• Integrating Reuse Block 
• Working with Component Browser 
• Changing Components in DEHDL 
• Searching for Information on Schematic and Navigating Signals 
• Working with Properties 
• Working with Groups
• Adding Wires and Signal Names 
• DEHDL Viewing and Tools Options 
• Working with Project Manager

Thanks to Henk for his work in helping DEHDL designers become more efficient in utilizing our products!

Please share your experiences in viewing and utilizing the content available in these new videos.

Jerry “GenPart” Grzenia

The 16.6 release of OrCAD Capture has a couple new productivity enhancements centered around how reference designators are assigned to components in the schematic.

Read on for more details …

Design Level Auto-Reference Designator Assignments
In 16.6, in addition to the schematic level annotation of reference designators, you can also perform a design level annotation by selecting the Design Level option:

The previous releases were limited to annotations at only the schematic level. There is also a schematic level auto reference for PSpice. Note that the part reference is the reference number plus the designator, and the 16.6 release insures that the reference and the part reference are always in sync.


Locking Reference and Designator Properties
You can now set the newly added “Preserve designator” and “Preserve User Assigned Valid References” in the Annotate window to preserve the values of designators and reference designators that you have modified:

The user modification to any reference is detected and marked by Capture.

I look forward to your feedback in using these new capabilities.

Jerry “GenPart” Grzenia

The Allegro PCB Editor 16.6 ‘Show Measure’ command now displays results in database and alternate units.  Alternate unit display requires the enablement of the user preference variable ‘showmeasure_altunits’. ‘Show Measure’ also supports a measurement between padstacks even if a common layer does not exist. This will be helpful when measuring mask-related geometry to conductor.

Read on for more details …

Open the User Preference Editor as we need to enable the variable for dual units. Setup – User Preference Editor – Display – Element:

 

Select an alternate unit of your choice; for example ‘millimeters’:

 

Invoke Display – Measure or use the icon    then make an adjustment to the find filter that aligns with your intended selection (pins, shapes, etc). Note the dual unit display in the report window:

 

Measure two elements originating on different layers. For your convenience, there is a soldermask shape just below the Xhatch area:

 

I look forward to your input on this new capability.

Jerry “GenPart” Grzenia

The Add Connect with Offset command in Allegro PCB Editor 16.6 is designed to primarily address the requirement to route with non-standard angles to help minimize impedance discontinuities while routing across fiberglass substrates. Other routing applications may be applicable as a result of this implementation, including, but not limited to, package/connector breakout or routing associated with tester cards.  

The Offset Routing command is integrated into the standard Add Connect command and is available in all Allegro product options.  

Options

• Route offset mode: Checkbox for "Add Connect" to use the route offset angle
  • Default setting = Off
• Route offset angle: A two-decimal fill-in field for entering the offset angle
  • Default setting = 10.00 degrees
  • Range = 4 to 18.5 degrees
• Line Lock: Must be set to Line = 45
  

 
Function Keys

• TAB key: Use this system-defined key to switch between a soft bend (first angle increment) and a hard turn (second angle increment). Each time that you hit the tab key, it will flip to the other angle.
• funckey a ‘pop flip’: Consider creating a user-defined function assignment to help you toggle between conventional and offset routing. The letter ‘a’ is used as an example only.

The 16.6 Allegro PCB Editor now has IPC 2581 data transfer capabilities. Thanks to Ed Hickey – the Allegro Sr. Product Engineering Manager - for preparing this information below.

Read on for more details …

IPC 2581 Overview

PCBs have changed significantly over the past three decades, yet to the surprise of many, we still commonly use 30-year-old ways of communicating design intent to manufacturing. These decades old data-communication formats were originally conceived to drive the emerging numerically controlled machines. The Gerber format, properly implemented, is perfectly adequate to transfer image data, but it does not transfer stackup data, materials, design intent or netlist.  IPC, the trade group, has been aware of the challenges and dynamics of the PCB design and manufacturing segment and has been an ardent advocate for the replacement of old data-communication formats.

In early 2001, iNEMI (the International National Electronics Manufacturing Initiative) stepped in to lead a broad, industry-wide project to define the definitive data exchange convergence specification. The goal was to enable accurate, efficient data exchange between designers and manufacturers of printed circuit boards (PCB) and assemblies using a single XLM-based data exchange format. From this effort, an IPC committee developed a new standard, IPC-2581, Generic Requirements for Printed Board Assembly Products Manufacturing Description Data and Transfer Methodology; it was released in March 2004.

With IPC-2581, the industry finally has a global opportunity save millions of dollars by implementing a standardized safe and complete transfer of designs data and save millions of dollars wasted by managing multiple files in different formats. But as usual with data format specifications, nothing can be done until the supply chain produces, consumes and supports such a specification. This is where a new consortium of PCB design software (EDA) and supply chain companies fits in: to bring companies together to enable, facilitate and drive use of IPC-2581.

The Consortium website is - http://ipc-2581.com/


IPC 2581 Export

The IPC 2581 Export tool is invoked through the File-Export-ipc-2581 menu. IPC 2581 may also be exported through a command window as IPC2581_out.  When run from the Allegro PCB Editor the IPC 2581 Export tool is shown as follows:

 The items located in this form are described as follows:
o    Output File Name: The file name of the exported file. Default file extension is .cvg. A browser to point to a specific directory is next to the file name field. Current board drawing name is defaulted.
o    Version: The available export version options. There are currently 2 versions available:
      - IPC2581-A :  Latest Revision A released March 2012
      - IPC-2581-1: Amendment I, initial Allegro implementation.
o    Output Units: The output units may be set regardless of the current design units. There are three available units, inches, millimeter, and micron.
o    Function Mode and Level:

       
         
      - Full Mode: The FULL mode identifier incorporates a total of fifteen functions. Each function is represented and available in the file. The order of the details in the file is not significant as several elements may be used to address any given function. Hierarchical padstack and route information reflects original design intent that may be altered in the representation of the flattened fabrication data. For FABRICATION and ASSEMBLY, flattened data will be used
      - Design Mode: The DESIGN mode consists of three levels of complexity. Each level performs a different function consisting of an original design starting from scratch to completed design that had already been converted to manufacturing data, or a completed design that is still in the CAD format structure. See IPC 2582 and IPC 2583 for sectional data descriptions.
      - Fabrication Mode: The FABRICATION mode consists of three levels of complexity. Each level describes information in a layered format, from very simplistic data to that where the customer has dictated very specific materials and material stack-up structures. See IPC 2584 and IPC 2588 for sectional data descriptions.
      - Assembly Mode: The ASSEMBLY mode consists of three levels of complexity. Each level describes a concept of more complete information. The simplest level is mainly bill of material data as well as external copper layers. In its most complete form, the assembly information describes the component approved vendor listing for aliases and substitution in sufficient detail to ensure proper assembly. See IPC 2586 and IPC 2588 for sectional data descriptions.
      - Test Mode: The Test mode consists of three levels of complexity. Each level describes a specific function for testing information that must be contained within a file. In its simplest mode, the data describes information to allow bare board testing. In its most complex mode, there is information on in-circuit test, impedance control, and dielectric withstanding voltage conditions. See IPC 2585 and IPC 2587 for sectional data descriptions
      - Function Levels: The IPC 258X is limited to be organized as one of thirteen function levels. The level attribute, when associated with the mode attribute, defines the complexity and detail of the file content.
       •    The level attribute consists of a positive integer and identifies complexity with respect to the characteristics for mode-DESIGN, mode-FABRICATION, mode-ASSEMBLY, and mode-TEXT. A mode- FULL consists of all the elements for an IPC 258X file and has only one (1) level value. For all other modes, the level attribute relates to the type of mode and is apportioned as one of three levels.
      - Export Selection: The Function Mode and level select the default data type extractions for export, but the user may add or remove specific data types by selecting the check-box next to that item.
o    Film Creation…: This Invokes the Artwork Control Form where film record Classes and subclasses are assigned to a film record:

 

      - Contained within the film record form is a Domain Selection button. This is used to assign specific film record layers to specific outputs. Any film that is to be exported through the IPC 2581 must be selected in the IPC 2581 column. If the film record is not selected, the file record will be ignored during the export process.
o    Layer Mapping Edit…: This maps all of the film records to specific data layer type expected in the IPC 2581 file. All layers must be mapped to a layer type definition. If a layer is not mapped to a layer type, it will be ignored during the export process.
      - Artwork File: The film record name to be exported (derived from the Allegro CLASS/SUBCLASS for outer copper layers, inner layers, documentation layers, solder mask/paste layers and miscellaneous image layers).
      - Outer Copper layers: maps the film record to the outermost copper layers
      - Inner Layers: maps the film records to internal conductor layers, signal and/or plane layers.
      - Documentation layers: maps film records for fab drawings, assembly drawings, etc to documentation type layers.
      - SolderMask, SolderPaste Layers: maps the film records as masking type layers for Solder and Paste Masks.
      - Miscellaneous Layers: maps the film records as undetermined type of layer data, such as silk screen, etc.:

o    Export Properties (tab) – Defines the properties to be exported to IPC 2581. These are net and component properties, typically used in 3rd party analysis applications.  This property export list creates an ipc2581_attr_config.atr (property configuration) file which lists these properties and is a reference though the export tool.
o    Zip file – compress the IPC 2581 text file
o    Vector text – export the text characters as line segments.
o    Export – begins the export of the board drawing to the IPC 2581 format.

Note:  When creating new film records, by default, the new film is linked to four domains (Artwork, PDF, IPC 2581 and Visibility). The Artwork Control Form -> Domain Selection allows the user to enable or disable film records for the desired application. See Film Domains for more information

IPC 2581 Flow:
1.    Invoke the IPC 2581 export tool ( File->export->IPC 2581)
2.    Change the export file name and location if desired
3.    Invoke the Artwork Control Form (Film Creation) and create film records for each film layer if not previously defined.
4.    From the Film Control Form, Invoke the Domain tool. Verify all layers to be exported to IPC 2581 are selected.
5.    Close Domain form. Close Film Record Form.
6.    Invoke the layer mapping tool (Layer Mapping Edit…). Assign each exported film record to a layer type.
7.    Select options for Vector text and/or Compress output files as needed
8.    Run export (Export)
9.    When completed, view the log file, and close the IPC 2581 Export form. If no errors were found, the file is created.

IPC 2581 Export Command Line

IPC 2581 may be Invoked from a command line entry in a Windows cmd prompt or terminal window.  The command name is IPC2581_out. There are various required and optional command line arguments.
    ipc2581_out [-ufdblRnpstcgeyzDOIMS] [-g <attr_file>] [-o <output_file>] <brd

    REQUIRED ARGUMENTS:
        <brd>:  Name of the design file.

    OPTIONAL ARGUMENTS:
-u:  Output units.  The Allegro unit of measure.  Valid args: INCH, MILLIMETER, MICRON. default: INCH (INCH/MILS), MILLIMETER (METER/MILLIM/CENTIM), MICRON (MICRON)
-o:   Output file name.  Default: <drawing>_ipc2581
-f:  Version. IPC2581 format revision to write. Valid args: 1.00, 1.01(v1.00 with Amendment 1), 1.02(IPC2581-A) default: 1.02
-g:  Property configuration file.  ASCII text file that specifies the property name for component and net.  The file format is as follows:

               Component/DFA_DEV_CLASS_UD
               Component/DFA_DEV_TYPE
               Net/DIFFP_PHASE_TOL_DYNAMIC
               Net/MAX_VIA_COUNT

-d:  Device descriptions. Default: off
-b:  Bill of Material (BOM). Default: off
-I:   Layer stackup.  Default: off
-R:  Drill layers. Default: off
-n:  Net list.  Default: off
-p:  Component package. Default: off
-s:  Source tool. Default: ‘CadenceTool’
-t:  Device land pattern. Default: off
-c:  Component descriptions. Default: off
-D:  Documentation layers. Default: off
-O:  Outer copper layers. Default: off
-I:  Inner layers. Default: off
-M:  Miscellaneous image layers.  Default: off
-S:  SolderMask/SolderPaste Legend Layers. Default: off
-e:  Export vector text. Default: off
-y:  Export cross section data only.  Default: off
-z:  Zip file. Default: off

    Example 1: Generate IPC 2581 file ‘test.cvg’ which contains Allegro objects on outer copper layers, inner layers, documentation layers, miscellaneous layers, and solder Mask/solderPaste layers, which are defined via the UI ‘Layer Mapping Edit’:

                   ipc2581_out test.brd -o test -O -I -D -M -S

    Example 2: Generate IPC 2581 file ‘test.cvg’ which contains net list, package, and component description with output units MILLIMETER:

                  ipc2581_out test.brd -o test -n -p -c -u MILLIMETER

IPC 2581 Import

Allegro provides the ability to import the artwork films, but they must be generated from the Allegro tools. When the import tool is Invoked, the user selects the IPC 2581 file and selects the import button. As the artwork data is imported. As part of the import, new Manufacturing subclasses are created using the film record name prefixed with ‘ipc-’
Example: Film record name = Int_1_pwr
        Manufacturing subclass name = ipc-int_1_pwr
Once IPC 2581 data is imported, the compare button in the IPC 2581 In form is enabled. When this button is selected a user interface is Invoked. The imported layer may then be compared to the film record subclass layers:

 
The IPC film layer name is listed on the left side of the form, and the layer visibility check box is located under the column labels IPC. The Film Column displays the corresponding film record. By selecting the checkboxes, the IPC layer and film record visibility may be toggled off and on. The IPC check box also enables a color change pallet when selected with the right mouse button.
Should the import be unable to correspond an IPC layer to a film record, or incorrectly match an IPC layer to a film record, the browser button located to the far right side of the form provides a form to select a film record to correspond with the IPC layer:

This compare utility provides a visual compare ensuring all artwork data is complete, based on the film record export. Another capability is the ability to import IPC 2581 data into a previous version of a drawing, and visually compare changes from one version of a design to another.

Film Domain 

Artwork films can now be designated by domain where they appear. There are four domains available; Artwork, PDF, IPC2581 and Visibility.  Access the User Interface by clicking on ‘Domain Selection’. One of the benefits of the domain form is the ability to segregate films for artwork vs. films for PDF out:

Please share your experiences using this capability.

Jerry “GenPart” Grzenia

The 16.6 release of Allegro PCB Editor has several new enhancements for team design work (design partitioning) that help reduce the number of .DPF (design partition file) import/export iterations the PCB Design team experiences in the physical team design flow.

Flexible Boundaries
Designed to reduce the number of iterations between the master and partition designers, it’s now possible for partition designers to move components or route signals outside their respective boundaries. The master designer controls whether boundaries are flexible by the enablement of a new workflow manager option called "Soft Boundary". This behavior is an "all-or-none" situation for the team. Partition designers do not have the ability to control this behavior. Prior to 16.6, components could always be moved outside the boundary of a partition to allow the user more space to work in the partition, but when the partition was exported back to the master designer, components outside the boundary were ignored. When soft boundaries are enabled, those components moved outside will now be saved during the export.

Constraint Editing
Partition designers are now permitted to edit physical, spacing, and electrical constraints. The master designer controls whether constraint editing privileges are granted to the team by the enablement of a new workflow manager option called "Edit_cns". Similar to the flexible boundary enhancement, this behavior is an all-or-none situation. Partition designers do not have the ability to control read/write behavior of constraint entry.

ECO Wizard
Available in the workflow manager, the ECO wizard is designed to help streamline the process involving new netlist submits. This entails importing all outstanding partition databases, netlist import, then re-export of partition files.

Below are some details and screenshots that highlight the new 16.6 design partitioning capabilities. The example considers a design that has been setup with two partitions (partition_2 and partition_3). In order to utilize these features, you will need to use the team design product option:


In the Workflow Manager selected from the Place > Design Partition menu, you can enable partitions 2 & 3 for export, enable the "Edit Cns" and "Soft Boundary" options, and enable "Suppress Mail":

 
When viewing the partitioned database, it’s easy to determine what elements are owned by the respective partition designer by the intensity level of the graphic display. "Owned" elements appear is the normal display, whereas "un-owned" elements are dimmed:

 
The enablement of soft boundaries allows a specific partition designer to move components and to route across the boundary and connect to the pins of the components that are owned by your partition. For the condition of a connection sourced from an owned pin terminating to an un-owned pin, if there is a desire to route this connection, you will not be able to snap the route to the pin location. Consider using either Add Connect or Slide to position the route end point at the terminal location. Otherwise, you can leave the route as dangling for the master designer to complete.

You can have a condition where two designers are editing the same constraint object. In our example, you can enable Partition_2 and Partition_3 then click "Cns Report" located in the lower right of the form. This report will provide a constraint differences summary between the master and partition file:

 
You can use the tree widget in the left pane to review the differences:

and then import Partition_2 and Partition_3:

With respect to the constraint edit change that impacted both partitions, the order in which the partitions are imported back to the master determines which edit is accepted. In the case where both partitions were enabled for import, Partition_2 would take priority based on the ordering within the workflow manager. "First in, wins" best describes the conflict resolution technique.

Please share your experiences with these new 16.6 features.

Jerry “GenPart” Grzenia

• You will not be allowed to place these components on the outer layers as a result of the components having the ‘dual_sided_component’ property applied
• When initially moving any of the resistors from the placement list, they will automatically drop to the embedded layer (SIGNAL_4). There is no RMB action necessary when the component has a ‘required’ property value and there is only one embedded layer identified in the stackup.
• The component pads are suppressed when using ‘Indirect Attach’ method
• You should see 2 indirect symbol vias on SIGNAL_4

Just a short post today.

In the 16.6 Allegro PCB Editor release, multiple region shapes can now be assigned to a single region constraint object. Using the General Edit Application mode, pre-select multiple region shapes, then use the context-sensitive RMB menu to access the Assign to Region command.

Ensure you are in General Edit Application mode. Consider an example where we will assign the region shapes associated with the components U7 and U8 to a "BGA" region constraint object.

Window-select the two purple region shapes, or hold down the CONTROL key, then select each shape individually. Hover over any one region shape, then RMB—Assign to Region. Select "BGA" from the list:

 


I look forward to your comments!

Jerry “GenPart” Grzenia

• All instances of the net will be renamed to a new name
• All properties and constraints captured on the net instances retained
• All membership to net objects are retained

The net rename capability is available as:

• A menu command
• A context (RMB) menu command
• Change of a net name
• Using the Attribute Editor
• Using the Change command
• As a DEHDL console command:

    _netrename <old_net_name> <new_net_name>

I look forward to your feedback on this capability.

Jerry “GenPart” Grzenia

The signal integrity (SI) prophets had predicted this time would come, and it turns out they were right. The techniques that SI engineers have been using for the past decade to analyze multi-gigabit serial link interfaces are now starting to be applied to parallel memory interfaces, such as DDR4. And it all makes sense.

Back when PCI Express initially came out at 2.5Gbps, we saw a seismic shift in how simulation and analysis would be done, forever changing the SI landscape. The requirement to evaluate eye diagrams derived from huge bit streams of 10,000 bits or more pushed traditional circuit simulation into a characterization role, and convolution-based channel simulators came on the scene to handle the new high-capacity simulation needs. The need to efficiently model equalization effects, including real-time adaptation, gave rise to executable "algorithmic" models, and a new capability called "AMI" for "Algorithmic Modeling Interface" was driven into the industry-standard IBIS specification. Those were exciting times in the SI world, and Cadence was out in front leading the pack (see Interrogating the chips in this 2007 EE Times article).

Serial link analysis techniques such as bit error rate (BER) with bathtub curves, high-capacity simulation, and eye diagrams are now part of memory interface analysis.

Now we have fast-forwarded  into a new era, and the memory interfaces we are dealing with today are looking eerily "serial linkish". The data rates we see for DDR4 data buses today are right where we were initially for PCI Express. DDR4 I/O structures are similar to what we have historically had in the SerDes space, with built-in pullup termination on-die, and nicely linear, symmetric, well-behaved output impedances. While signaling is still single-ended, data buses have moved closer towards point-to-point topologies, with more use of "clamshell" component placement on top and bottom of the PCB to cluster loads at the end of the transmission line when possible. And while equalization has still eluded off-the-shelf memory devices (largely for cost reasons), on the controller side of the interface we are seeing feed-forward equalization (FFE, i.e. pre/de-emphasis) becoming more and more common.

In addition to taking on serial link characteristics, the techniques used to analyze DDR4 are also shifting towards those traditionally used in serial links. Data bus compliance and timing for DDR4 has shifted from traditional cycle-by-cycle setup and hold criteria to a mask-based compliance, as commonly used with SerDes devices and serial links. Also, DDR4 JEDEC specs now specify a target BER; "The design specification is BER<1e-16 ... BER will be characterized and extrapolated if necessary using a dual dirac method ..." These are exactly the same types of specifications that serial link interfaces have been using for years.

So where does all of this lead us? Cadence Sigrity SystemSI - Parallel Bus Analysis has integrated the serial link channel simulation engine in, and successfully applied it to coupled, single-ended parallel buses, even including non-ideal power effects (patent pending). What does this bring us? First, it brings us simulation capacity, so you now have the unique ability to run hundreds of thousands or even millions of bits of traffic through the memory interface, way beyond the capacity of traditional circuit simulation. This lets you see what the eye is really going to look like in the lab, when you are sampling many, many bits worth of data on your oscilloscope. This also enables deterministic and random jitter to be injected, so you can see what effect that will have on the eye.

AMI modeling comes along for the ride as well. Once channel simulation is introduced, you are also free to use AMI models for the equalization used at the controller. FFE modeling used with serial link applications can be directly leveraged for controller equalization, and comprehensive AMI models are included with Sigrity SystemSI.

But fundamentally what all this simulation capacity and modeling enables is generation of a very detailed eye distribution, from which (with dual dirac statistical post-processing) bathtub curves can be produced, just like with serial links. The bathtub curves provide the key insight into the BER performance of the interface, which at the end of the day is what you really need to know as an engineer, whether you are working on parallel memory interfaces or serial links.

Grab a cup of coffee and watch the demonstration of our complete solution that uses channel simulation to perform BER analysis on DDR4 interfaces with Cadence Sigrity SystemSI - Parallel Bus. If you come from the SerDes space, a lot of this will look familiar to you, just as those new DDR4 specs probably do. But hey, as they say, what's old is new again. And just like before, Cadence is out in front.  As a wise man once said, unless you're the lead dog of the sled team, the view doesn't change much.  

Tell us about your experiences using SystemSI and Cadence Sigrity modeling and extraction technology.

Team Allegro 

The Allegro Design Workbench Team Design Option (TDO) offers two (2) specific integrator roles for team design and collaboration:
Logical design integrator
  Responsible for front-end design
Physical design integrator
  Responsible for back-end design

A logical design integrator or physical design integrator needs to enable Team Design and assign and inform team members to work on the design project from the list of designers.

Read on for more details…

Logical design integrator (LDI)

The LDI has complete permission on logical objects as defined in the design and assigns users to logical objects of the design. The physical objects are shown as read only for an LDI and by default the LDI sees the logical hierarchy. The Team Design interface displays the schematic design in a hierarchical form. It shows all the blocks and its logical objects such as:
Schematic
Symbol
Package

 


Physical design integrator (PDI)

The PDI has complete permission on physical objects as defined in the design and assigns users to physical objects of the design. The logical objects are shown as read-only for a PDI and by default the PDI sees the Physical Hierarchy. The Team Design interface displays the physical design in a parent/child hierarchical relationship.  It shows all the blocks and:
Physical view
Collections
Partitions
Modules
Package view


 

TDO User Model

A team of users is assigned for ECAD projects - the users are assigned either using LDAP or the template file. The user doing ETD is either the LDI or PDI or both, based upon either the LDAP or the template file. All project users get read-only permissions on a design. Users working on particular design objects get read and write permissions on design objects within a project based upon user assignment.

TDO pulls out user IDs from the corporate LDAP system, and the LDAP query and filter are controlled using the ldap.config file under cdssetup.

When the teamassignmnettemplate.xml file is placed in the proper directory, and the environment variable is defined, the project team assignment phase will access the team assignment template, providing a list of the user IDs defined within the template.


What do you think about this capability?
Jerry “GenPart” Grzenia

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Exposing metal through solder mask openings is as necessary as it can be frustrating. For regular arrays and grids of pins of a flip chip, embedding the openings directly in the padstack definition for the bumps is perfect. But, what about for wire bond designs?

Fingers and power/ground rings need to be exposed so they can be bonded to, but visibility of surrounding metal should be minimized. At the same time, it is important that the openings themselves not have sharp corners which could cause manufacturing concerns like the mask getting peeled back.

As a result, it is not appropriate to use the solder mask pads in the finger pad definitions (which wouldn't help with the rings, regardless!). Instead, a smooth mask outline around sets of fingers in close proximity is the best approach.

How, then, do you go about making this happen? With the Cadence APD and SiP Layout tools in 16.6, the answer is the bond finger solder masking tool. Keep reading to learn more about what this handy tool allows you to do.

Creating Clean Solder Mask Openings

Near the end of your initial design of a substrate for a package with one or more wire bonded dies, it comes time to define the solder mask openings. APD and SiP Layout provide you with a tool specifically to accomplish this task. You can find it under the Manufacture -> Create Bond Finger Solder Mask menu item. 

With a simple interface (see for yourself, below!), you get all the controls that you need. There are two modes to give you the flexibility you need, with different options for bond finger exposure and power/ground ring openings. 

When creating mask openings for fingers, you should take special note of the field at the very bottom. By controlling the intent width, you can eliminate any potentially sharp corners on the inside of the mask shape between fingers. This way, you get a smooth, clean opening around an entire tier of fingers with one simple selection.

Conversely, for bonds to your rings, you can expose only the pieces of the ring which have bonds to them. The mask openings can even be trimmed to the edge of the shape to make sure no nearby clines are accidentally exposed.

Do you have a need to create these types of masks around a set of vias on your substrate layer? Do you have some pins, perhaps, where using the padstack-embedded solder mask pad shape is not suitable? Fret not. Turn on the "icp_soldermask_allow_pins" option in your User Preferences editor and you can define masks for these objects with the same settings you have when masking traditional fingers. How's that for flexibility?

What If I Need to Move My Bond Fingers After I've Generated My Shapes?

Fear not! ECO and design revisions are a fact of life. When you receive an order that requires changes to the bond finger pattern, you can make those changes knowing that, when complete, the mask openings can be quickly and easily updated.

Using the same manufacturing command, make sure that you have the "Delete existing solder mask" option enabled at the top of the options (it is on in the screen shot above). This will automatically delete the old shapes as you select the fingers you have moved or added, leaving just the new mask. This ensures that you don't have overlapping masks that could result in undesirable outlines or - even worse - the exposure of clines and vias that are where one or more of the old fingers used to be.

What Tools Are Available for Validating My Solder Masks Are Correct?

Once you have your solder masks defined (or after updating them because of a design change request), it is important to validate that only the right objects are going to be exposed during manufacturing of your substrate.

The APD and SiP Layout tools provide you with a number of checks beyond the basic solder mask online DRCs. You can configure these under the Assembly worksheet in Constraint Manager and run them from the Manufacture -> Assembly Rules Checker... command, shown below with the 16.6 solder mask rules:

If you want to write your own checks, you can use the RAVEL tool to define custom rules. Or, for pure visualization of the metal exposed by the solder mask shapes (particularly useful for documentation purposes), you can use the layer compare tool set, which we covered in an earlier entry in this series. By doing a logical AND between the solder mask layer and the corresponding substrate conductor layer, you can create a layer showing only the metal that is visible through holes in the solder mask. There's even the option of viewing things in the 3D Viewer, where you can see the bond wires and their clearance from the masks as they get close to the substrate! Talk about choices!

How Do You Define Your Solder Masks?

Armed with these tools, are you eager to make your design flow more efficient? If you have an idea for how to make these tools even more powerful, we would love to hear it. Give your Cadence support representative a call and let us know your ideas. Just don't be surprised if, with the next software release, you see your idea realized in the tool!

Jeff Gallagher

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A test point is a location within an electronic circuit that is used to either monitor the state of the circuitry or to inject test signals. Test points have two primary uses:

• During manufacturing they are used to verify that a newly assembled device is working correctly. Any equipment that fails this testing is either discarded or sent for rework.
• After sale of the device to a customer, test points may be used at a later time to repair the device if it malfunctions, or if the device needs to be re-calibrated after having components replaced

A test point can be a simple pad on a net, a through hole, or a pin where test equipment can be connected. Figure 1 shows a test point on a via.

Figure 1 - Test point on a via

The application note discussed here helps you understand the test point flow from OrCAD® Capture to Allegro® PCB Editor and vice versa. This document explains different ways of defining test points in OrCAD Capture and transferring these to Allegro PCB Editor. The application note also explains how to identify nets on which a test point is to be defined in Allegro PCB Editor.

Defining Test Points

Test points are used in PCB boards for testing signal continuity. They are added in the PCB board itself to verify the circuit or to provide test input signals. Allegro PCB Editor allows defining test points on nets, vias, and pins. However, in recent times, it has been observed that schematic engineers have expressed the need of defining test points in the front-end schematic itself. Owing to their knowledge of circuit and critical signals/nets in the design, schematic engineers wish to identify the net on which test points should be added on the PCB board.

This document discusses how you can define test points on nets in the schematic. You can take either of the following two approaches:

•   Identify the nets on which a test point is to be added
•   Filter off the nets on which test points are not added, allowing Allegro PCB Editor to choose all other nets for Testprep. This is done by defining the NO_TEST property.

Defining Test Points in Allegro PCB Editor

In Allegro PCB Editor you can define test points directly even if it is not defined in the schematics. A test point is generated in Allegro PCB Editor using Testprep. Testprep adds test points on nets which do not have NO_TEST property defined on them.

In Allegro PCB Editor, while using Testprep you can assign the following properties:

• NO_TEST: Attach to nets that do not require test points. In Allegro Constraint Manager, this property is specified as Prohibit.
• TESTPOINT_QUANTITY: You can limit the number of test points that will automatically be added to the net using this property.

The two properties, NO_TEST and TESTPOINT_QUANTITY, are displayed in Allegro Constraint Manager as shown in Figure 2.

Figure 2 - Allegro Constraint Manager showing test point properties

Refer to the following document for details on running Testprep:

http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:DocumentViewer;src=dt;q=cspb_board_design/testpoint.pdf

Defining Test Points in Schematic

You can either directly define test points on nets in the schematic or identify the nets on which test points are to be added in Allegro PCB Editor.
The following sections explain the different methods of defining test points in schematic.

By adding a single pin component

Place a single pin component on the net in the schematic design on which the test point is to be defined. This single pin component can itself be treated as a test point in Allegro PCB Editor.
The footprint (PCB Editor Symbol) of this component can be a pad which will be placed on the net and work as a testpoint.

Figure 3 - Single pin component used as a test point

In the example test case, the TP_SinglePinComponent directory has a schematic and its board file, which uses a single pin component as a test point. A sample single pin component and its footprint (pad) are also present in it.

By adding property ‘NO_TEST'

As discussed above, Testprep adds test points on nets which do not have NO_TEST property defined on it.

You can identify nets on which a test point is not to be added by defining the NO_TEST property on the nets in the schematic design. To add NO_TEST in Capture, select the nets, open property editor, and click New Property to add a property with the following details:

NAME=NO_TEST

Value=YES

NO_TEST defined in schematic is transferred to Allegro PCB Editor as a net property. You can also add or delete this property from nets in Allegro PCB Editor.

Backannotating Test Point Properties to Schematic

The board designer can define or modify the NO_TEST property directly on board in Allegro PCB Editor before running Testprep to add testpoints. This information is transferred to the schematic through back annotation.

As discussed in Defining Test Points in Allegro PCB Editor , while using Testprep you can assign the following properties in Allegro PCB Editor:

• NO_TEST
• TESTPOINT_QUANTITY
• TESTPOINT_ALLOW_UNDER
• TESTPOINT_MAX_DENSITY

Among these properties, NO_TEST and TESTPOINT_QUANTITY are defined on nets and can be back annotated to the schematic. For this, make sure that the properties are set to YES in the allegro.cfg file under the [netprops] section.

TESTPOINT_ALLOW_UNDER and TESTPOINT_MAX_DENSITY cannot be back annotated to the schematic as these are defined on symbols in Allegro PCB Editor.

Refer to the app note here for the detailed step-by-step procedures on the complete flow, including a test case attached to the app note.

Note: The above link can only be accessed by Cadence customers who have valid login credentials for Cadence Online Support (http://support.cadence.com).

Naveen Konchada
Cadence Customer Support

The Allegro Design Entry CIS (OrCAD Capture) 16.6 release provides extensions to the Design Rule Checks (DRC) system. The Custom DRC provides the ability to extend the Capture DRC system to user-defined rules.

Open an Allegro Design Entry CIS design database (.dsn) file, select a design in Project Manager, and click menu Tools > Design Rules Check:


Click on Configure Custom DRC:


The following DRCs are provided as examples:

• Hanging Wires
• Device Pin Mismatch
• Overlapping Wires
• Reference Prefix Mismatch
• Port-Pin Mismatch
• Shorted Discrete Part

Enable all DRCs to execute, select the checkbox “Run Custom DRC”, and then select OK to execute DRC. Here’s an example output:

All TCL code for the DRCs above is available in <$CDSROOT>\tools\capture\tclscripts\capDRC.

In the schematic, you can select any DRC and use RMB Waive DRC:


The DRC is added to the Waived DRC list and does not show on the schematic canvas anymore.

In the DRC form, you can use the Selection Filter for a group of DRCs: Use Menu View > Selection Filter followed by clearing all checkboxes except “Markers”. Select a group of DRCs and waive them. Rerun DRC with “Preserve Waived DRC” checked:


All waived DRCs remain hidden. Use Select Filter to un-waive a group of DRCs in an area. Use RMB > UnWaive DRC. Now run DRC again with the checkbox cleared for “Preserve Waived DRC”—all DRCs should reappear.

As always, I look forward to your feedback!

Jerry “GenPart” Grzenia