Legacy material editors supported different file formats leading to inconsistencies across PCB and package substrate design applications. This drawback due to inconsistency is now overcome by the new Material Editor that uses a ...(read more)![]()
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BoardSurfers: Managing Materials Using A Single Material File for PCB, Package, and Simulation
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(P)SpiceItUp: Simulation Profiles in Five Steps
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Boardsurfers: An Introduction to Allegro DesignTrue DFM Rule Aggregator
Design companies often work with multiple PCB fabricators and each fabricator may have a different set of DFM rules. It is a customary practice followed by design companies to create a common denominator rule set that can be applied to all fabricator...(read more)![]()
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BoardSurfers: How to Install Allegro ECAD-MCAD Library Creator Server?
In addition to reducing package creation time by 60-80%, Cadence Allegro ECAD-MCAD Library Creator has the Library Creator repository, which provides thousands of ready-to-use packages and templates. The repository allows centralized configuration-controlled storage...(read more)![]()
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BoardSurfers: Managing Materials Using A Single Material File for PCB, Package, and Simulation
Legacy material editors supported different file formats leading to inconsistencies across PCB and package substrate design applications. This drawback due to inconsistency is now overcome by the new Material Editor that uses a ...(read more)![]()
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BoardSurfers: Training Insights: Running RAVEL Rules from Command Line
In one of the previous posts, we learnt about How to Run a RAVEL Rule from the GUI. The RAVEL rules that you write can be run from command line or Graphical User Interface (GUI) of Allegro® PCB Editor. You can also run these rules from Allegro&re...(read more)![]()
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(P)SpiceItUp: Five Ways of Finding the Right PSpice A/D Component
When you are designing a schematic, you want to focus on the accuracy and performance of the circuit, and not spend time looking for and comparing various components on vendor websites. The integrated part search and placement feature in the OrCAD&re...(read more)![]()
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Designing the Allegro System Capture Way
A design starts in the mind of an architect, gets drawn on whiteboards as basic block diagrams that describe a system. Next, designers see what can be reused from older designs, schematics get drawn, parts are identified, from in-house libraries or from online vendors. If the available parts don’t match their requirement, librarians are asked to create or modify parts. Then checks and rules are run to ensure design integrity. Teams work together on a large design. Libraries are updated, flags go up on the designers’ screens telling them newer parts are available, or someone has made changes. They sync their changes. Different versions are maintained for the entire design or even the parts used. Variants are created for different costs or geographies. Finally, the logical design gets done and is converted to a netlist, and layout files are made. Routing and layout experts come into the picture and, ta-dah! the design is ready for fabrication.(read more)![]()
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BoardSurfers: How to Create and Remove External DRCs using SKILL in PCB Editor
Design rules checks (DRC) determines whether your layout design complies with design constraints and highlights any violations. Performing DRC is an essential step of PCB development signoff before you generate manufacturing files. With increasing mi...(read more)![]()
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BoardSurfers: Managing Materials Using A Single Material File for PCB, Package, and Simulation
Legacy material editors supported different file formats leading to inconsistencies across PCB and package substrate design applications. This drawback due to inconsistency is now overcome by the new Material Editor that uses a ...(read more)![]()
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BoardSurfers: Training Insights: Running RAVEL Rules from Command Line
In one of the previous posts, we learnt about How to Run a RAVEL Rule from the GUI. The RAVEL rules that you write can be run from command line or Graphical User Interface (GUI) of Allegro® PCB Editor. You can also run these rules from Allegro&re...(read more)![]()
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(P)SpiceItUp: Five Ways of Finding the Right PSpice A/D Component
When you are designing a schematic, you want to focus on the accuracy and performance of the circuit, and not spend time looking for and comparing various components on vendor websites. The integrated part search and placement feature in the OrCAD&re...(read more)![]()
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The Year That Was: Cadence PCB Design Blogs in 2020
And what a year it has been! Like many of you, we've worked from home. We juggled house and office work, washed our hands innumerable times a day, rinsed every grape before putting it in the fridge, and scrambled to look presentable in conference...(read more)![]()
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Cadence OrCAD and Allegro 17.4-2019 HotFix SPB17.40.013 is Now Available
The HotFix 013 (QIR 2, indicated as 2021 in the application splash screens) update for OrCAD® and Allegro® is now available at Cadence Downloads. This blog post contains important links for accessing this update and introduces some of the mai...(read more)![]()
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(P)SpiceItUp: Generating ISO 7637-2 Standard Pulse 2a in PSpice A/D
Many times, you would have required to create a standard pulse waveform that can be used for testing devices as per the industry standard.
One good example is to simulate the ISO 7637-2 transient at the schematic design stage. This practice ensures t...(read more)![]()
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ASCENT: Ready, Steady, Design ... Even With Existing Libraries
After a quick overview of Allegro® System Capture, let’s start at the very beginning of the design process. Where are the parts? What parts can you use when creating an Allegro System Capture logical design? Parts, as you know, are the basi...(read more)![]()
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BoardSurfers: Installation Know-How: Using Third-Party Tools with Cadence OrCAD and Allegro Products
The add-on model is applicable everywhere! You can choose a basic version of the car and add-on products make it faster, nicer, or more special. Air travel add-on includes seat reservation, food, priority check-in, and extra baggage. When you purchas...(read more)![]()
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BoardSurfers: Training Insights: Setting Up and Using Pin Delays in Constraint Manager
Pin delays are used to specify the time delay or length from the internal package connection to the pin’s mounting layer. It is critical to include pin delays when tuning high-speed nets to ensure signal performance. Pin delays are used in the ...(read more)![]()
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(P)SpiceItUp: Search by Category, Description, or Function with PSpice Part Search
As a designer, your requirement at the early stages of schematic design is quite different, that is the part information you need when it comes to implementing the schematic design and while simulating it for testing and analysis is different i...(read more)![]()
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ASCENT: Finding the Right Parts with Unified Search
Some people say that finding the right components for a design is the most time-consuming part of designing. If that is correct, you need all the help you can get to quickly locate what you need. You might need a specific type of component, a specifi...(read more)![]()
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