Using Sensitivity Analysis of PSpice

I was thinking of writing a series of blogs showcasing what all ammunition's a circuit designer may need to deal with any complex circuits today. So, here's the first one. 

When in college, books tell you everything about your circuit. You already know which components are critical in your designs. But, what about when you enter an industry? You have completely new designs that you build or come across and you need to know which components are critical for your measurement goals. The first thing a designer has to be sure of is to thoroughly understand/ know their circuit. 

In the first Tech-Blog of this series, we will take a sample RF Amplifier circuit and perform PSpice Sensitivity Analysis on it. Read more into how this Advanced Analysis capability helps you reduce circuit design costs considerably.

Continue Reading on PSpice.com

Anyone who designs complex circuits and claims they don’t use the Optimizer on their design is most likely a super-genius with an IQ of 250. Sure, most of you have used the Optimizer on your circuit before. But, have you used it in combination with Sensitivity Analysis? Optimization is just like having infinite monkeys at your disposal. Use it properly and you're The Man, abuse it and you're wasting time and resources.

With the combination of Sensitivity Analysis and Optimizer tools you avoid:

• Prototype revisions (Direct cost)
• Prototype revisions (Opportunity cost)
• An extra week in Engineering (vs using Optimization)
• Releasing an inferior design

In this Blog 2 of the Tech-Series, we will use the Optimization tool on the same RF Amplifier circuit from Blog 1 for shortlisting the critical components in the design. But, now we focus on increasing this design's productivity! Learn how to use these tools together and make the most out of your own designs.

Continue Reading on PSpice.com...

Most of the PCB designers I know are creatures of habit just like I was...

we have our favorite colors, layer names, customized keyboard and our number one goal is to see how many nets we can route in one day. Very rarely do we change – but when we do it’s either because we changed employers or we are forced to because the tried and true processes don’t work any longer.

Can you relate?

Those of you who were fortunate enough to attend past CDN Live conferences may remember that, as a customer I used to present a session called “Allegro Tips – Did you know … ? In all fairness, my presentations were called that because I was an Allegro user, but having joined Cadence roughly two years ago I have come to hear from and appreciate the many loyal OrCAD users out in the community that are creating some bleeding edge designs.

So, back in early 2016, at the last CDN Live Silicon Valley edition, we revived this very informative session – at least that is what some of you told us – but this time with a new name – “Cadence PCB Editor – Tips & Tricks – Did you know … ?” As a secondary piece to this revival, we are also starting a similar blog that hopefully will give all users of Cadence PCB Editors valuable tips and tricks that may make you stop and think about different options open to making your design process faster and easier and hopefully more productive. Change can sometimes be good for you.

Therefore, without further ado, with my opening blog, I offer up to you, our valued readers, Vince’s Favorite Usability Features from V17.2-2016. We hope you find them very informative and helpful. Check back soon for additional PCB-related blogs.

1: FbQ – Find by Query

We introduced a new and powerful relational query engine in the V17.2 QIR1 release. You can use FbQ to easily and quickly locate design objects within any size of design – large or small. With a few simple clicks, users can create, use, save and recall time saving queries.

Have you discovered how powerful this new feature can be?

2: Customizable Visibility Pane

We enhanced the Visibility Pane to allow designers more efficient access and control of layer content. Instead of a single stackup approach, the Visibility Pane now gives you quick access to different Zone stackups if you are designing rigid-flex PCBs. This pane now has the added benefit of being able to control layers other than electrical.

Customization of the Visibility Pane is done from the Visibility Pane tab in the Color Dialog.

Using the Visibility Pane Configuration settings, a user can tailor the Visibility Pane to their liking by turning on/off the following information rows:

• Global Visibility
• View Selection
• Layer Stackups Selection*
• Layer Conductors
• Layer Planes
• Layer Masks

*Note: Stackup Selection with the Layer Stackups dropdown will only be available (for turning on or off) in designs that contain more than one zone in the stackup.

You can also configure which columns to display in the Visibility pane. Simply drag and drop or use UP arrow to add classes to the Visible Classes sections so that they are visible on the Visibility Pane.

"Board Geometry” added in the above step is now added to the Visibility Pane.

Use the sliders to control the size of the color boxes as well as the spacing between the color boxes on the Visibility Pane.

Slider to control color boxes:  

Smallest button size with largest spacing:                                                

Largest button size with smallest spacing: 

Color control made easy. Let us show you how!!!

3: Layer Select Mode

We enhanced the Visibility Pane to allow the user to go into “Layer Select Mode”. This action puts the canvas into a “single layer” view and allows the designer to quickly view or scroll through each of the layers available in the Visibility Pane. When Layer Select Mode is enabled, the layer names change to blue HTML links.

HTML links allow users to switch from one individual layer view to any other. Simply click on any of the Layer Names and the canvas will change to that particular layer.

When in Layer Select Mode, any combination of multiple layers to be selected and viewed using CTRL+Layer to select.

Trying to find routing channels for those last few hard to get in connections?

Use the power of Layer Select Mode to help you!!

4: FbQ & Multiple Copper Shapes

We improved dynamic shape parameters to enable users to select multiple shapes and view, edit or assign parameters, which will then apply the changed settings to each shape. Users also have the option to reset all parameters to the Global Default settings with a single click. Using SHIFT or CTRL + Click to select multiple shapes, performing a RMB in QIR 1 gives users an enhanced "Parameters” selection (as shown on the right screen shot – the left screen shot is pre-QIR 1.

The Parameters dialog for multiple selected shapes has been enhanced to indicate the information that is different between the selected shapes and what settings have been changed from the Global Shape Parameters settings.

But the real hidden power of this new feature is to combine it with the power of FbQ– which we discussed earlier in this blog. Simply use FbQ to isolate the required copper planes, select those planes from within the Matching Objects pane and then use the RMB to access the Parameters dialog. Make the necessary changes and apply them to all of the selected copper shapes at once.

How easy is that! 

5: FbQ & 3D Canvas

Another feature that the power of FbQ can be harnessed to promote is the new 3D Canvas. This new 3D Canvas has taken our previous 3D Viewer and added intelligence. Additionally, unlike some other tools that make designers function either ONLY in the 2D space or the 3D space – but not both at the same time – we have re-written the 3D Canvas so that it can be visible, functioning and even more surprising to some – communicating with the 2D canvas.

If you find this intriguing, stay tuned for a future dedicated blog on our new 3D Canvas. In the meantime, allow me to once again demonstrate how two very different features of Cadence editors can be brought together to make the power of two even more productive for designers.

Using FbQ designers can easily select any critical routed traces and then invoke the 3D Canvas to review those routed traces in 3D. See them traverse layers and see them with their attached pads and pin padstacks. How cool and beneficial is that? You can do the same thing with components – either from within the PCB Editor canvas or from within the Symbol Editor tool. Now users can take advantage of the 3D canvas to visually confirm that their components are created correctly.

We hope you have found this blog helpful. Please check back periodically as new and related blogs will be added by our very experienced and resourceful team.

Thanks again and we look forward to your next visit.

Happy designing !!

Related Links

• Back to “10 Top Reasons to Move Up to Allegro 17.2-2016 Release”
• Related material on "What’s New in Allegro" on Cadence.com
• See our YouTube Cadence Allegro Channel and the following "ease of use" video.

www.youtube.com/watch

Every year Cadence Design Systems an industry leader in the Electronic Design Automation Industry hosts worldwide CDNLive forums where Cadence technology users and technical industry experts showcase their latest innovations using Cadence technologies associated with designing Digital ICs, Mixed-Signal ICs and PCBs.

This year at CDNLive Silicon Valley from April 11^th to April 12^th the PCB simulation session track is showcasing PSpice simulation-focused presentations by Texas Instruments, Spero Devices, MathWorks and Cadence. Topics for this year include

• Improving design manufacturing yield and reliability
• Process improvements on PSpice model integration within the Spectre Circuit Simulator
• Customization of the web-based Texas Instrument power supply design simulator with Allegro PSpice Simulator
• Algorithm to Implementation: Combining MATLAB and Simulink with PSpice to streamline PCB design
• Innovative Memristor technology leveraged with PSpice CMOS Analog Co-Processor for Acceleration of Performance Computing Applications

Click here to register.

For more innovative technologies being leveraged with PSpice, check out http://www.pspice.com/

Jerry "GenPart" Grzenia

I love that recently Westerns movies are making a comeback. Something about the romanticism of a hired gun coming in with no baggage, looking at the situation pragmatically, and doing what everyone knows needs to be done, but just can’t.

Once Upon a Time in the West and The Good, the Bad and the Ugly, Sergio Leone’s epic Spaghetti Westerns, aren’t the only foreign influence on what we think of as American Westerns.

Some might say that the greatest Western ever was Japanese director Akira Kurosawa’s Seven Samurai. The plot is simple: a small village harassed by criminal bandits, hires seven warriors to fight them off. Sound familiar?

The hired warrior isn’t afraid to kill a few bad guys. And then they leave and peace is restored. Japan has long had the concept of a hired gun. The characters 助っ人 (suketto) in Japanese are ‘helper person’ and are used to describe many situations, even PCB design.

They do what the regular team can’t—or won’t—do, but everyone knows needs to be done. I like to think that sometimes our PCB design teams work the same way.

Designs are getting so complicated that it’s rare to find someone who knows everything about everything and can do it all alone. So we have our in-house suketto or hired guns.

These experts that can come in, quickly assess the problem, do what needs to be done and get out so that the rest of us can get back to our regular lives.

But there’s a problem. PCB design isn’t shooting a couple of bad guys. Everyone else doesn't hide in the church, we all need to keep on designing.

That means we can’t divvy up a design into segments because the lines of your domain and mine are not geographical, they’re technical. My buddy is the expert in DDR4 high-speed routing, but I still have to do my work while he’s helping me out.

This situation is pretty common with lots of our customers. They have teams around the globe and many domain experts scattered throughout the teams. They came to us for a way to leverage these talents without disrupting design projects, locking down files, or involving IT.

Now, our customers have a distinct advantage over their competition. They have hired guns taking out the bad guys for them all while shortening their design time.

How much shorter?

Check out this handy calculator we put together and find out how much time you could be saving.

When you push more of your board into high-performance design fabric like an SoC, suddenly you have the scope for differentiation and innovation in an SoC that you design yourself. Custom SoCs increase differentiation, reliability, IP protection, security of supply, and performance. They also decrease board size, power, BOM, and cost. Are you ready to take the leap?

Many companies are working with custom ASICs these days. Sensor companies making their sensors smarter and OEMs integrating discrete components with a CPU for smaller PCBs and more reliable, lower cost products.

Is a Custom ASIC in Your Future? Watch this Informative Webinar to Get the Answers

ARM and Cadence recently held a live webinar on the topic of custom ASICs. Phil Burr, Senior Product Manager at ARM and Ian Dennison, Senior Group Director at Cadence gave an expert presentation on the benefits of custom chips, the routes to creating your own chip, and the tools and services available to make custom chip development easier with lower risk and cost.

If you are a start-up, an IoT developer, a sensor or mixed signal company, or an enterprise new to SoC looking to differentiate your product, watch this webinar to get an idea on how to safely and cost effectively create your own custom ASICs.

If you would like to learn more about the ARM DesignStart program or the Cadence Hosted Design Solutions, go to the Accelerating IoT System Design tab under the ARM-Based Solutions page on cadence.com.

Interested in an easy-to-use, collaborative, and robust design-environment that reduces design cycle? Use, Cadence® Allegro® and OrCAD® release 17.2-2016.  Here are the 10 Top Reasons to Move Up to Allegro 17.2-2016 Release This enables you to accelerate your PCB design cycle. 

Get started immediately with the new release using the central page on https://support.cadence.com. It lists important links to Allegro and OrCAD 17.2-2016 documents. Visit the “one-stop shop" page to get all you need to install and use the release.

Visit the page - https://support.cadence.com/SPB172launch

These pages list What’s New, videos, application notes, migration guide, and other online help documents. In the left pane, select Getting Started for release-level information or select a product (for example, Allegro PCB Editor) for information about it.

Allegro PCB Editor

Allegro Design Entry HDL

Allegro Design Entry CIS (OrCAD Capture)

Allegro AMS Simulator (PSpice)

Visit the page - https://support.cadence.com/SPB172launch for more.

Contact us for any questions. Leave a comment in this blog post or use the Feedback / Like mechanism within https://support.cadence.com.

Happy New Learning!

~Jasmine

Every year Cadence Design Systems an industry leader in the Electronic Design Automation Industry hosts worldwide CDNLive forums where Cadence technology users and technical industry experts showcase their latest innovations using Cadence technologies associated with designing Digital ICs, Mixed-Signal ICs and PCBs.

This year at CDNLive Silicon Valley from April 11^th to April 12^th the PCB simulation session track is showcasing PSpice simulation-focused presentations by Texas Instruments, Spero Devices, MathWorks and Cadence. Topics for this year include

• Improving design manufacturing yield and reliability
• Process improvements on PSpice model integration within the Spectre Circuit Simulator
• Customization of the web-based Texas Instrument power supply design simulator with Allegro PSpice Simulator
• Algorithm to Implementation: Combining MATLAB and Simulink with PSpice to streamline PCB design
• Innovative Memristor technology leveraged with PSpice CMOS Analog Co-Processor for Acceleration of Performance Computing Applications

Click here to register.

For more innovative technologies being leveraged with PSpice, check out http://www.pspice.com/

Jerry "GenPart" Grzenia

I love that recently Westerns movies are making a comeback. Something about the romanticism of a hired gun coming in with no baggage, looking at the situation pragmatically, and doing what everyone knows needs to be done, but just can’t.

Once Upon a Time in the West and The Good, the Bad and the Ugly, Sergio Leone’s epic Spaghetti Westerns, aren’t the only foreign influence on what we think of as American Westerns.

Some might say that the greatest Western ever was Japanese director Akira Kurosawa’s Seven Samurai. The plot is simple: a small village harassed by criminal bandits, hires seven warriors to fight them off. Sound familiar?

The hired warrior isn’t afraid to kill a few bad guys. And then they leave and peace is restored. Japan has long had the concept of a hired gun. The characters 助っ人 (suketto) in Japanese are ‘helper person’ and are used to describe many situations, even PCB design.

They do what the regular team can’t—or won’t—do, but everyone knows needs to be done. I like to think that sometimes our PCB design teams work the same way.

Designs are getting so complicated that it’s rare to find someone who knows everything about everything and can do it all alone. So we have our in-house suketto or hired guns.

These experts that can come in, quickly assess the problem, do what needs to be done and get out so that the rest of us can get back to our regular lives.

But there’s a problem. PCB design isn’t shooting a couple of bad guys. Everyone else doesn't hide in the church, we all need to keep on designing.

That means we can’t divvy up a design into segments because the lines of your domain and mine are not geographical, they’re technical. My buddy is the expert in DDR4 high-speed routing, but I still have to do my work while he’s helping me out.

This situation is pretty common with lots of our customers. They have teams around the globe and many domain experts scattered throughout the teams. They came to us for a way to leverage these talents without disrupting design projects, locking down files, or involving IT.

Now, our customers have a distinct advantage over their competition. They have hired guns taking out the bad guys for them all while shortening their design time.

How much shorter?

Check out this handy calculator we put together and find out how much time you could be saving.

When you push more of your board into high-performance design fabric like an SoC, suddenly you have the scope for differentiation and innovation in an SoC that you design yourself. Custom SoCs increase differentiation, reliability, IP protection, security of supply, and performance. They also decrease board size, power, BOM, and cost. Are you ready to take the leap?

Many companies are working with custom ASICs these days. Sensor companies making their sensors smarter and OEMs integrating discrete components with a CPU for smaller PCBs and more reliable, lower cost products.

Is a Custom ASIC in Your Future? Watch this Informative Webinar to Get the Answers

ARM and Cadence recently held a live webinar on the topic of custom ASICs. Phil Burr, Senior Product Manager at ARM and Ian Dennison, Senior Group Director at Cadence gave an expert presentation on the benefits of custom chips, the routes to creating your own chip, and the tools and services available to make custom chip development easier with lower risk and cost.

If you are a start-up, an IoT developer, a sensor or mixed signal company, or an enterprise new to SoC looking to differentiate your product, watch this webinar to get an idea on how to safely and cost effectively create your own custom ASICs.

If you would like to learn more about the ARM DesignStart program or the Cadence Hosted Design Solutions, go to the Accelerating IoT System Design tab under the ARM-Based Solutions page on cadence.com.

Interested in an easy-to-use, collaborative, and robust design-environment that reduces design cycle? Use, Cadence® Allegro® and OrCAD® release 17.2-2016.  Here are the 10 Top Reasons to Move Up to Allegro 17.2-2016 Release This enables you to accelerate your PCB design cycle. 

Get started immediately with the new release using the central page on https://support.cadence.com. It lists important links to Allegro and OrCAD 17.2-2016 documents. Visit the “one-stop shop" page to get all you need to install and use the release.

Visit the page - https://support.cadence.com/SPB172launch

These pages list What’s New, videos, application notes, migration guide, and other online help documents. In the left pane, select Getting Started for release-level information or select a product (for example, Allegro PCB Editor) for information about it.

Allegro PCB Editor

Allegro Design Entry HDL

Allegro Design Entry CIS (OrCAD Capture)

Allegro AMS Simulator (PSpice)

Visit the page - https://support.cadence.com/SPB172launch for more.

Contact us for any questions. Leave a comment in this blog post or use the Feedback / Like mechanism within https://support.cadence.com.

Happy New Learning!

~Jasmine

Cadence Online Support has this Rapid Adoption Kit (RAK) on Rigid-Flex in Allegro PCB Editor 17.2 that introduces a flow to define unique stackups by physical zone. The Cross Section Editor in 17.2 has been enhanced to support multiple stackup definitions including support for mask and coating layers. The primary driver for this enhancement is Rigid- Flex applications where it’s common to have different fabrics across the final PCB product. Benefits will also be realized for customers designing standard Rigid PCBs. Soldermask and Solderpaste and their thicknesses can be added above/below the surface layers. Rigid PCBs may also require inlay material zones for RF/Analog circuits.

This RAK covers …

• Adding Non-Conductor Layers to Cross Section

• Multiple Stackup Entry

• IPC2581 Layer Functions

• Adding/Editing Physical Zones in the PCB Editor

Rigid-flex technology lets us create smaller PCBs than ever before. Watch the video on Serious tools for advanced rigid-flex

Cross Section Support of Non-Conductor Layers

The PCB Editor Database represents non-conductor layers as “Mask” or “Dielectric” although they may serve different purposes like coating or plating areas. To add a mask layer above layer Top, select the Top cell in the Cross Section grid then use the RMB to access the “Add Layers” command as shown in the graphic below.

The new Surface Finishes Class supports the following subclasses …

Multi-Cross Section Support

The Cross Section Editor has been enhanced to support multiple stackups, each capable of supporting conductor and non- conductor layers such as Soldermask and Coverlay. The Cross Section Editor provides total thicknesses for each stackup in terms of accumulated conductor layers as well as a mask layer option.

Multi-Stackup Grid

Layer Functions (IPC2581)

The Cross Section Editor now supports IPC2581 defined Layer Functions. These user selected Layer functions are defined as attributes in the IPC-2581 stack-up layer definition for fabrication instructions at the manufacturing level. Customers utilizing the 2581 standard for data transfer may want to consider these options. The diagram below reveals the full set of layer function options.

Dielectric layer types support the following options …

Physical Zones

Zones are physical areas in the design that map to one of the available stackups in the cross section editor. Zones are added using the standard add shape or add rectangle commands found in the Setup – Zones menu. Mapping a stackup to a Zone may occur at the creation of the Zone, or assigned through the Zone Manager after the Zone is created. Constraint Regions and Rooms may also be assigned to Zones at creation or through the Zone Manager.

When adding a Zone, you can loosely define the boundary during the creation command as it will snap to the design outline geometry upon completing the command. In the left figure below, a zone boundary is extended beyond the actual design outline. It eventually snaps to the actual design outline when the add shape command is completed.

Inter Layer Design Rule Checks

This RAK also explores Inter Layer checks that provide a new tier of checking of mask to mask and mask to other geometry types providing the user with problem detection earlier in the design to manufacturing cycle.

             In typical rigid-flex designs, various stackup definitions are assigned into different zones where the top or bottom level might differ zone to zone. In traditional workarounds, the package symbols require special attention to padstack definitions, special “flex” symbols, and so on, or use the embedded component process to place these symbols onto the correct layer for not only artwork purposes but for documentation as well. You may refer the document on Dynamic Zone Placement in Allegro PCB Editor 17.2  here. This reviews the PCB Editor's awareness of varying top surface layers in a multi-zone rigid-flex design during placement.

Click here for the Rapid Adoption Kit and for the detailed step-by-step procedures on the Rigid-Flex functionality, as well as various other aspects that are not covered in this blog.

Note: The above link can only be accessed by Cadence customers who have valid login ID for https://support.cadence.com

Related Links

Learning Advanced Flex and Rigid-Flex Design Support in Allegro 17.2-2016

Why Move Up to Allegro 17.2-2016? Advanced Flex and Rigid-Flex Design Support (Reason 1 of 10)

Cadence Allegro Rigid-Flex Overview on Cadence.com

Ensuring Reliable Products with New Rigid-Flex Design Rules

By John Burkhert Jr

The business world keeps score with dollars and cents. The overhead cost of layout and material cost of bare boards are a significant drain on capital. Face it; Printed Circuit Boards are expensive. The value that a Designer can add is to reduce the overall cost of boards. If not for that, the enterprise could put a CAD license on anyone’s desk and let them have at it. Just imagine if CAD tools were easy to use! That day may come so we are well advised to find other ways to earn our keep.

One job featured a flexible circuit called “the Hydra” on account of the various connectors forming a serpentine hairdo for the central rigid section

Giving educated advice on system architecture is one possible avenue. We know the boards, the parts, the connections and enough about the hardware to be an asset to the Physical Design. The layout function has unique insights on how a flex circuit can be as simple as a ribbon cable or as complex as a vehicle’s entire wiring harness. The depth, breadth, and value of PCB design is what you make of it. Some of that knowledge can contribute to the overall picture in terms of the number of PCBs in a system.

Things to consider when combining boards:

• Complexity - matching the technology in terms of stack-up and architecture
• Power - similar voltages and noise floors
• Edge rates, resonant frequencies - victim vs. aggressor traces coexisting.
• System wide connections - are the endpoints in similar locations for a flexible solution.

Image credit: Author - can you find the 15 edge connectors?

Chromebooks For The Win

Designing the PCBs for Chromebooks was my main occupation for years, so I’m comfortable using laptops as an example. The trick with laptops is that so much is happening on the screen side of the hinge. All of that information needs a wide pipeline to the keyboard side. Beyond the display itself, we also have a camera module, RF antennas and maybe even a row of colored LEDs for decoration. Power and data have to squeeze through the hinge for all of those things. Their locations are hardwired, but a long, skinny circuit across the top could incorporate cameras, microphones, printed antennas and various sensors.

Image credit: Author - a bit of work went into the row of lights on the case.

Under the keyboard, there may be a few opportunities for unification. Assembly and serviceability are the primary concerns at the end of the line. In the meantime, getting the heat out is the engineering challenge. The bare minimum Main Logic Board (MLB) has the System On Chip, (SOC) external memory, the Power Management Integrated Circuit (PMIC) and connectors. A plethora, make that two plethoras and one bevy of connectors that mostly connect to bespoke flex circuits. A lot of meetings took place regarding the optimum topology for this product.

Keyboards, trackpads, and batteries have standard connectors, but the path from the unit to the MLB aka “motherboard” varies, and so does the standard cabling lengths. The other goodies usually require custom flex circuits. This is where you need to get creative.

One job featured a flexible circuit called “the Hydra” on account of the various connectors forming a serpentine hairdo for the central rigid section. Another one had an acronym, tROtS for “the Rest Of the Story”. The ROS board was the catch-all for the functions that didn’t make it onto the main PCBs of the system. It does not have to be an all-in-one solution to help. A two-in-one strategy employed in a couple of places puts the math in your favor as well. Turning 12 boards into 10 is a win.

Pile On

Looking back at the MLB, a fair number of functions were brought on board including WIFI (under the can) and the audio just to the right by the lower USB 2 connector. That little chip drove this board from a 1+N+1 stack-up construction to a 2+N+2 which was a cost hit. It was also a relief that the extra layer of micro-vias improved the DDR routing to those four devices at the top of the board. Fun stuff when you add a 0.4 mm pitch BGA to the mix. Ideally, any new parts will not drive the PCB to a higher technology level. Trade-offs are a part of the game.

Image credit Christopher Ross - Fully loaded with batteries, speakers and heat spreaders.

The board itself was essentially poured into the space between the fans and the lower chassis. The back side has headroom for the very smallest parts only. Many of the sensors as well as the NFC are on-board while the GPS and microphone array are on their own flex or boards. Our goal was to get as much on this 10-layer board as possible.

A lot of what looks like open space is reserved for things like the heat pipe and cabling. That Intel SOC radiates big time, so we went all in to make a cool Pixel with all of that power. I’d say it worked out pretty well as Google products go. It received solid to glowing reviews and few actual buyers. Other Chromebooks did the heavy lifting on the raw numbers side. I see this same thing playing out with the Pixel phone too. Samsung and others will continue to make the Android phones and Chromebooks while Google makes (M)ad-money on its core business.

The Wrap

Whether your business is small or large, the benefit of a reduced Bill of Material is undeniable. Simplifying labor and increasing reliability are two side benefits. The main cost is in up-front engineering. It’s expensive to create a solution that is acceptable in both coexistence and functionality. Someone who has been down in the trenches between the traces can really be beneficial to the Industrial Design and/or Product Design teams. Put those insights to good use to help your company’s bottom line and expand your toolkit.

By John Burkhert Jr

I want to take you back to a project that highlights a few twists as all good projects will. 17 years ago I was presented with 20 pounds of potatoes and a 10 pound bag. The bag was shaped like a PEZ dispenser with a crown of gold fingers in place of the plastic head. The actual name of the early form factor was XENPAK. It used the XAUI protocol which has become a  popular 10G-for-the-masses deal. My piece of the puzzle sat between the fiber optic backbone and the edge routers that supplied data to medium and large enterprises.

That inside-out effort lead to an “It’s not you, it’s us” story about how they didn’t need anything from us for a while.

As an aside, Cisco accounted for about 80% of the merchant market for these transponders. The “merchant market” is the part where the industry is not doing that layer in-house. A small company filing a socket for a huge company is a pretty common scenario. The big guy  sneezes, and you get pneumonia for roughly 13 weeks. They liked our stuff and ordered a lot. Then we delivered, possibly beyond their expectations. That inside-out effort lead to an “It’s not you, it’s us” story about how they didn’t need anything from us for a while. Food for thought on how the big manipulate the small. They did award us a technology alignment award for our flagship product – just before canceling our quarter on the 10G part – so we had that going for us, which was nice; sort of.

Photo Credit: Opticore - Typical XAUI based 10G device

The Thick (or Thin) of the Plot

Back in that simpler world based in the weeks before 9/11, a good laser and photodetector were some chunky components. The special goodness we were adding was a device that reduced chromatic dispersion, whatever that is, and it allowed us to double the distance between repeater stations along the fiber network. This component was my first exposure to 0.5 mm pitch devices. This pitch, if you didn’t already know, is the threshold where micro-vias become a thing. Mid 2001 was still early-adopter times for HDI, so I definitely had the fab-shop on speed-dial.

These high-performance parts can blink a laser on and off 10,000,000,000 times in a second while reading the blinks from another laser at the same bit rate. When you ask this much of your equipment, it will inevitably end up with an exothermic reaction; toasty IT closets for everyone! We had to check that problem with active cooling. We put a Thermo Electric Cooler (TEC) right between the transmit and receive chains. You will find these TEC devices in the portable coolers that plug into those strange, round, 12V power ports they put in cars. Ok, most of us know them as cigarette lighters. The point is that the “friggin’ laser” and the detector, along with their insatiable appetite for LC filtering, had us over-committed on component placement by about 50%. Call it 7.5 pounds of potatoes and we have to stop short of mashing them together in the PEZ dispenser.

The Squeeze Is On

Connectors were also going through the fine-pitch revolution. We found a stacking connector that gave us a one-millimeter clearance between the top of the lower board and the bottom of the upper board. Not exactly the kind of space PCB dreams are made of. The connector itself needed about ⅓ of the board space on one side of the mother as well as the daughter. If the space of one board is equal to one, the net space after the connectors across two boards comes out to around one and a half.

Feasible, in theory, if you can make good use of the one millimeter between the two boards. It was at this time that I began putting the component height on the layer that defines each footprint’s X and Y extents. This is useful information to have whenever the board’s overhead space is at a premium. A one-millimeter tall inductor would result in zero head-room in that corresponding area on the other board. It wasn’t as though either side could have half of the headroom and pull this off. The contours of one define the limits of the other.

Splitting the Schematic

Breaking up the circuit came down to one characteristic: the 10G path had to come and go on the bottom board. There was no RF, no micro-vias, and no selective gold finish on a regular four-layer FR4 daughtercard. I still recall that the vendor had no DFM issues on the cheap board. My manager at the time had no tolerance for feedback from the fabricator. He read those calls and e-mails as documentation or engineering failures. We typically read them as standard line width and material negotiations. You can thank that nameless but brilliant man for all those times I’ve told you to get your stack-up approved ahead of the routing gate.

Moving Right Along

The newly minted daughter card was only smaller than its parent by the mom’s gold fingers. Removing everything we possibly could and squeezing through an interactive placement of shared headroom was just enough to pull it all together. It was a small company called Big Bear Networks, and I had one PCB Layout contractor on board with me. The layouts would be super dense because we would use the same core circuit for the XENPAK DWDM and a couple other transceiver form-factors. Overlap the three outlines, and only the common area is for component placement. In this way, we could deploy different SKUs using the same basic circuit.

Given such tight confines, I challenged the contractor, and we both tried to complete the placement within the common area. I was still trying to place the last two parts when he completed his version. Nearly all of his shunt elements were facing the edge of the shield with the ground pin out. It lengthened the inductive loops a bit but gave that extra sliver of room. His version also sent a segment of the 10G TX line to an inner layer. Mine was an outer layer solution with all of the shunted elements rotated with their ground pins towards the transmission line. I wanted everything with no compromise. Anyway, full stop. The consultant completed his lower board while I generated the upper board using an imported image of his placement for reference.

Image credit: Finisar - X2 form factor, one of the smaller Multi-Source-Agreement platforms for XAUI.

Winner, Winner, Chicken Dinner!

The boards came in, everything fit and the thermal readings were under control. The engineering samples had beautiful open eye diagrams, and the big Cisco order followed. You know the rest except the part where I eventually left this operation to flip the bit back to analog and rejoin previous management at a new company with a wider customer base. Then, as now, the valley (and the world) thrives on new ideas. Keep up your skills and keep getting those design wins.

By John Burkhert Jr

Bringing a multiboard system together is a chance for the designer to spread their wings. As the circuit spreads, so do the risk of crossed signals. Some of the ways the circuits can get scrambled include:

• Some connector vendors have clear indications of polarity. Others leave all numbering to the buyer. In the same way, a row of gold fingers will be anything we draw up in terms of pin numbers and signal names.
• While the physical design typically depicts the orientation of a connector by indicating the location of pin one, rarely is the net that goes on the circuit defined at that level.
• Each board in the system has a separate schematic, probably drawn up by a subject matter expert that naturally varies from one board to another.
• A connector can be mirrored to the secondary side, yet we can view it as though we had Superman X-ray vision.
• A single large connector can have a cable or flexible circuit that mates to it but then splits the larger connector’s signals into several smaller connectors that get distributed all over the system. Each of those branches will have a pin-one of its own but only one of them at the end where everything is collected together.
• Rogue changes on one card can derail a system.
• Library inconsistencies and simple mistakes can as well.
  

Closing all of those potential open loops takes a degree of organization. The system level physical designer is very concerned with everything fitting together. PCB Designers are working within their outline(s) and can also become a bit myopic in that regard. It seems as though we go over these things ad nauseam in the early design reviews when the high-level architecture is being laid out. Then, some bug crops up when we put everything together. What happens? How can we stay on an even keel?

Block it All Out

I don’t mean therapy or hitting your head against the wall. Block Diagrams, Wiring Diagrams, Interconnect Diagrams, Interface Control Diagrams, Outline Drawings, and beautiful 3D renderings all help put the big picture in perspective. They may also be considered too mundane for the critical path and be put off until everything is completely defined. What happens then is that any disconnects get cleaned up in the pre-production run. New boards/cables/flexes are rushed out and all of the expediting and long days go into trying to mitigate the risks before going to mass production. Turning up volume production on something that is mostly tested and verified is one way to live on the edge. So is blindfolded paragliding. Nobody talks about the time their parachute didn’t open. Fewer mistakes in the prototype stage pay the dividend known as peace of mind as we confidently scale up our efforts.

The bigger the job, the more we need to employ risk management in the form of stronger documentation. Nobody does testing and documentation quite like NASA, but the auto industry is really good at supply chain management. When you become part of the supply chain, you quickly become well managed. You get to generate all sorts of documents related to design verification at all levels. Just as you are managed, you become a technical manager to your suppliers as they do for theirs. But I digress.

Creating Order From Chaos, One Step at a Time

The thing is that this level of scrutiny is not as common in the typical consumer hardware setting. Getting your engineering folks to draw up a proper interconnect table may be a stretch. Starting your own “quick and dirty” version is better than nothing and may even prompt the team to fulfill their ideal destiny. We’re after a schematic of schematics. There is a lot of abstraction at this level. A box represents a board, and a list in the box represents the functional connectivity between the various boards.

Image credit: Research Gate - Use more or less detail as required

A system power tree is another important reference point. The number of functions a product has will be a close indicator of the different number of power domains required. Let’s say, for instance, that we have a camera and a display to go with a microphone and speakers to make an Arduino conference room package. All five of those items will want their own power supply even when they are designed for the same number of volts. Scale up to the devices with over 1000 pins and each little area of the device wants a particular power source all its own. They give me an 800-page owner’s manual for the Intel Skylake device. You’d shake your head at that ball-map. It does have an excellent power tree along with the reference design material though.

Life on the Analog Frontier

We got the chance to create a reference design for a Samsung Chromebook Plus. We had the main logic board and a handful of outlying boards. GPS, for instance, needed a quiet area so it could receive the small signals from the satellites. I mean quiet in an electromagnetic sense. The speakers still qualify as a problem because of their magnets. The metal enclosure, the WIFI, the Bluetooth and a number of sensors were all problems.

Coexistence is the name of the game when we try to make all of these disparate functions work together. Simulations will take us a long way, but there are blind spots. You don’t know until you have everything packed into the form factor and turn it all on. Who can forget the time that people wrapped their hands around the upper area of the new iPhone and were told that they were “holding it wrong”? The Pixel phone with its band of non-metal color is an indication of where the invisible connections are taking place through various antennas.

The short answer is that wireless connectivity is the risk that is hardest to manage. For the most part, we try to contain electromagnetic waves. In this case, we’re making them on purpose. The more wireless protocols you have, the more corner cases to explore. Life is better if you only have to tame one radio. Your phone is a war zone of conflicting interests. This laptop was no different. The prototypes were not 100% ready for prime time. The project was pulled together with a few schematic revisions including more filters and regulators; small stuff for the P1 stage except for mis-wiring the battery connector! Mass production followed on with minimal drama. I can say that now, but I was 10,000 miles from where most of the action took place. I know they worked hard too.

Image credit: Author - You’d think we could do something as simple as a battery connector.

The result was thin, light, fast, robust and flexible enough to wrap itself into a tablet, stylus included. Here is a glowing video review of the hardware. Spoiler: the man spent 12 minutes talking about this one laptop and did not have any negatives. Could it be that good? The awards at CES ‘17 were long and strong. This is the ARM processor version that has a lookalike big brother with the Intel SOC. The reviews tend to reflect that this is the lower tier of the Samsung premium convertibles. Working with the outside vendors on the reference designs was interesting.

They provided very detailed .dxf files so we could import geometry directly to the layout. The inner workings of the laptop were rendered over several layers. In a way, that was even better than drawings. The ODM (original design manufacturer) also had the wherewithal to take on the system interconnect review. Between the software models and mock-up hardware, the away team executed a nice product on a three-spin development cycle. Prototypes are the breadboard version without any physical limitations. Pre-production is the first time all of the components are joined in the form factor, and the third cycle is the one that you can still buy. Or not. I have pride in the work but, Samsung doesn’t share anything with me. They are in-house for their designs anyway. We provided a six-layer option to their eight.

Image credit: Author - The P1 version of a motherboard for a laptop/tablet chromebook

Great systems start with solid documentation, strong communication, and trust that everyone is going to hit their mark. The first iteration is to see if things work. The second is to see if it fits and the third has to have 100% of both of those things. In the words of the cold warriors of ancient times, “Trust but verify.” Multiboard systems are expected to be complicated by their nature. The different voltages have to be over- and under-powered in different combinations and over varying temperatures and so on. With all that is expected of these costly systems, it is incumbent upon the designer to take care that the system level connections are fully vetted before the die is cast.