Today’s wireless and high-speed chip designs integrate an incredible amount of functionality on very small silicon real estate. Such integration requires optimization from the early stages of the design to post-layout vs. schematic (LVS) signoff. Increasingly complex designs and advanced process nodes test the limits of electromagnetic (EM) solvers in terms of modeling capacity and times.
This blog highlights key points in the recent webinar, “Chip-Level Electromagnetic Crosstalk Signoff Using EMX Solver that presented a seamless, “EM-aware” chip design flow. The flow starts with the synthesis and optimization of passive components using EMX Designer, followed by floor-planning optimization with “EM in the loop” analysis of coupling effects using the EMX 3D Planar Solver’s black-boxing feature. These topics have been covered in previous webinars: Hierarchical Analysis of EM Crosstalk with EMX Planar 3D Solver and Passive Component Synthesis and Optimization for IC Design.
This webinar focuses on chip-level signoff of EM crosstalk using a seamless, unified design flow within Cadence Virtuoso Design Platform that combines the EMX solver for modeling parts of the layout sensitive to EM parasitics with the Quantus Extraction Solution for RC extraction for the rest of the circuit. This flow enables designers to de-risk their designs from unwanted EM coupling effects and achieve chip-level signoff for EM crosstalk.
RFIC – EM Signoff Flow with EMX Solver and Quantus Extraction
The Quantus Extraction Solution serves as a linchpin for designers to maximize their use of Rs and Cs on both digital-level and transistor-level flows, ensuring on-time tapeout deliveries. Combined with the EMX solver, you can select instances and nets and use the EM Solver Assistant to add them to the EM model and define the split layer for each net. You can then combine the EMX solver and Quantus results by running EMX Solver on partial layout (instances and nets) and stitch S-parameter results into Quantus Smart View.
Conclusion
The on-demand webinar provides details on the Virtuoso/EMX flow, including these takeaways:
- Single “golden” schematic/layout for implementation, verification, and EM analysis
- Seamless EM signoff flow with EMX Solver and Quantus for RFIC designs
- Fully automated electromagnetic analysis in Virtuoso Layout EXL
- Automatic layout pre-processing to reduce simulation runtime
- Integrated Virtuoso 3D Viewer to analyze current density and direction of current flow
The webinar also showcases an in-depth demonstration of a complementary metal oxide semiconductor (CMOS) amplifier design with inductors synthesized with EMX Designer and an LVS-driven net selection and Quantus SmartView stitching.
For more information on Cadence’s complete portfolio of multiphysics system analysis products, download the brochure.