At this year’s DesignCon, Meta held a session on ‘PowerTree-Based PDN Analysis, Correlation, and Signoff for MR/AR Systems.’ Presented by Kundan Chand and Grace Yu from Meta, they talked about power integrity (PI) analysis using Sigrity Aurora and Power Integrity tools such as PowerDC and OptimizePI.
The presentation covers some of the PDN design challenges in MR/VR systems, for example, the compact form factor, which limits the number of capacitors. There are also a number of PDN signoff challenges, such as the power system being very complicated, issues with design efficiency, and difficulties in viewing the whole power system.
To tackle some of these problems, Meta has been implementing Cadence tools. They mentioned that Cadence Aurora PowerTree was particularly helpful in:
- Finding problems earlier and preventing earlier late-stage changes that cause delays
- Enabling easy debugging and fixing of high current density, excessive IR drop, and missing vias
- Empowering non-PI experts, such as layout designers and EEs, to run a PI analysis before a PI engineer starts signoff analysis
Meta concluded that an Aurora PowerTree-based flow can be helpful in driving up efficiency in the product design cycle. It can prevent late stack-up change and signoff delays, and make ECO easier to track. For more about how Meta is using Power Integrity and Sigrity Aurora, click here to view their presentation.
Learn more about how you can get 10x design productivity with Cadence Sigrity Signal and Power Integrity.